stefan/kyupy
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54 Commits
Author SHA1 Message Date
stefan 8aa0f09254 logic_sim: better docs, deprecate LogicSim, move tests to newer classes 2026-06-21 10:09:45 +09:00
stefan c1ea05555e fix verilog tests 2026-06-21 09:26:51 +09:00
stefan 3a2cfb7788 techlib decides on cell type comb/dff/latch 2026-06-17 12:33:09 +09:00
stefan a28128830d beginning simple always block parsing in verilog 2025-11-27 21:19:59 +09:00
stefan fed66f85cb fix oob in test 2025-11-23 21:31:56 +09:00
stefan dd4e5c861a fix sim model generation for circuits with dangling nodes 2025-11-20 15:28:41 +09:00
stefan 31434cfd51 4v sim, fixed 6v sim, better testing 2025-11-09 08:09:46 +09:00
stefan 09420fd72c new logic sim interface prototype, simprim lib and test 2025-11-02 20:56:14 +09:00
stefan 3dfd0cb60d euivalence test, op format doc 2025-10-31 17:13:58 +09:00
stefan 9ca437fe47 fault injection for 4v sim, wave_sim test fix 2025-10-23 21:26:52 +09:00
stefan deb4599206 fix tests 2024-04-08 23:21:24 +09:00
stefan a4b7364478 mux21 in 6v logic sim, more test fixtures 2024-04-06 15:22:46 +09:00
stefan f6baf9cb5e a fast 6v sim 2024-04-05 23:21:59 +09:00
stefan 1a3b91c1c0 fix comment 2023-12-06 16:45:34 +09:00
Stefan Holst aa7536b8b0 line use and diff 2023-12-06 16:44:17 +09:00
Stefan Holst a6d1e4099c alap toposort, improve tests 2023-11-07 12:44:19 +09:00
Stefan Holst 4bb3f3424a cond in sdf parser. ignored for now. 2023-09-11 23:44:28 +09:00
Stefan Holst baeb759824 types, perf op growing list, keep s_nodes 2023-08-07 21:59:08 +09:00
Stefan Holst 967a232b1c fix pulse threshold selection 2023-07-29 09:45:48 +09:00
Stefan Holst 0ade89defa remove old test data, intro check 2023-07-22 15:58:16 +09:00
Stefan Holst 35e727e714 better docs, new techlib as default, fix tests 2023-07-22 13:11:11 +09:00
Stefan Holst 280c425486 fix test 2023-07-12 22:35:53 +09:00
Stefan Holst cf9a98b5ce del deprecated sdf code, explicit tlib use 2023-07-10 20:35:19 +09:00
Stefan Holst 5a693f7b9b preserve node order during resolve 2023-07-09 23:46:14 +09:00
Stefan Holst ea45a326ec add latch, fix xor delays, improve test 2023-07-09 13:42:07 +09:00
Stefan Holst d97555e9e9 fix simprim cells, add saed90 2023-07-08 18:55:52 +09:00
Stefan Holst afb0a64953 wsa accumulation in wavesim 2023-07-03 00:48:58 +09:00
Stefan Holst 670fb0b3fc circuit node substitution 2023-06-25 22:26:52 +09:00
Stefan Holst f8bf579be2 support concat, bus select, ISOL cells 2023-06-24 23:41:08 +09:00
Stefan Holst f61e2b42e8 support more cells in logic sim 2023-06-24 13:34:35 +09:00
Stefan Holst 0b15f9fa18 doc improvements 2023-06-19 17:05:39 +09:00
Stefan Holst dc76a9f517 new into demo 2023-06-19 14:01:31 +09:00
Stefan Holst 7a060b1831 support for static variations 2023-03-28 11:10:38 +09:00
Stefan Holst 44b0c887d7 random sampling of delays 2023-03-19 20:30:27 +09:00
Stefan Holst 5566b80e52 simprim, vat refactor, batchrange 2023-03-15 10:37:39 +09:00
stefan 1eb8d87884 faster logic sim, removing MVArray, BPArray 2023-03-12 23:59:10 +09:00
Stefan Holst 8da4a62bce switch to new wave_sim, silence occupancy warnings 2023-02-26 13:54:01 +09:00
stefan 3497bfdc75 first gpu-code, cached test fixtures 2023-02-26 13:09:49 +09:00
stefan f1ebe1487c new wave sim 2023-02-26 11:04:38 +09:00
stefan f0dac36ac7 interface -> io_nodes, io_loc fix 2023-02-24 21:56:29 +09:00
Stefan Holst d59d6401c8 fix stil loading and logic sim capture 2021-07-22 17:21:58 +09:00
Stefan Holst 387c436207 fix tests, version bump 2021-07-19 14:14:35 +09:00
Stefan Holst 0251d66d28 make circuit pickable and comparable 2021-03-28 19:35:19 +09:00
Stefan Holst 864230b883 initial letch support, fix capture in logic sim 2021-03-25 10:36:55 +09:00
Stefan Holst 62cf56e98a TechLib class, remove unnecessary .index 2021-01-16 13:17:18 +09:00
Stefan Holst ff4de6d782 de-lint and repr improvements 2021-01-12 15:32:18 +09:00
Stefan Holst 7f035c1ac5 Migration to new logic value representation 2020-12-21 19:16:52 +09:00
Stefan Holst 7bcfbf502b Documentation, cleanup, multi-valued logic 2020-12-20 17:44:04 +09:00
Stefan Holst 5830608527 Documenting circuit module 2020-12-18 21:14:00 +09:00
Stefan Holst a77ac4a397 start designing new data structures for m-valued logic 2020-12-14 14:06:18 +09:00