techlib decides on cell type comb/dff/latch

tests/test_circuit.py

@@ -2,7 +2,7 @@ import pickle
 
 from kyupy.circuit import GrowingList, Circuit, Node, Line
 from kyupy import verilog, bench
-from kyupy.techlib import SAED32
+from kyupy.techlib import KYUPY, SAED32
 
 def test_growing_list():
     gl = GrowingList()
@@ -155,7 +155,7 @@ def test_substitute():
 
 def test_resolve(mydir):
     c = verilog.load(mydir / 'b15_4ig.v.gz', tlib=SAED32)
-    s_names = [n.name for n in c.s_nodes]
+    s_names = [n.name for n in c.s_nodes(SAED32)]
     c.resolve_tlib_cells(SAED32)
-    s_names_prim = [n.name for n in c.s_nodes]
+    s_names_prim = [n.name for n in c.s_nodes(KYUPY)]
     assert s_names == s_names_prim, 'resolve_tlib_cells does not preserve names or order of s_nodes'

tests/test_logic_sim.py

@@ -3,7 +3,7 @@ import numpy as np
 from kyupy.logic_sim import LogicSim, LogicSim2V, LogicSim4V, LogicSim6V
 from kyupy import bench, logic, sim, verilog
 from kyupy.logic import mvarray, bparray, bp_to_mv, mv_to_bp
-from kyupy.techlib import SAED90
+from kyupy.techlib import SAED90, KYUPY
 
 def test_dangling():
     c = verilog.parse('''
@@ -105,7 +105,7 @@ def test_LogicSim6V_simprims(mydir):
     sim1.simulate(tests1)
     sim2.simulate(tests2)
     for loc1, loc2 in zip(c1.io_locs('o'), c2.io_locs('o')):
-        n = c1.s_nodes[loc1]
+        n = c1.s_nodes(KYUPY)[loc1]
         if (tests1[loc1] != tests2[loc2]).any():
             print(f'Mismatch at output {n}')
     np.testing.assert_array_equal(
@@ -287,7 +287,7 @@ def test_8v():
 
 
 def test_loop():
-    c = bench.parse('q=dff(d) d=not(q)')
+    c = bench.parse('q=DFF(d) d=NOT(q)')
     s = LogicSim(c, 4, m=8)
     assert s.s_len == 1
     mva = mvarray([['0'], ['1'], ['R'], ['F']])
@@ -314,7 +314,7 @@ def test_loop():
 
 
 def test_latch():
-    c = bench.parse('input(d, t) output(q) q=latch(d, t)')
+    c = bench.parse('input(d, t) output(q) q=LATCH(d, t)')
     s = LogicSim(c, 8, m=8)
     assert s.s_len == 4
     mva = mvarray('00-0', '00-1', '01-0', '01-1', '10-0', '10-1', '11-0', '11-1')

tests/test_stil.py

@@ -14,7 +14,7 @@ def test_b15(mydir):
     assert len(resp) > 0
 
     s2 = stil.load(mydir / 'b15_2ig.tf_nf.stil.gz')
-    tests = s2.tests_loc(b15)
+    tests = s2.tests_loc(b15, SAED32)
     resp = s2.responses(b15)
     assert len(tests) > 0
     assert len(resp) > 0