fix stil loading and logic sim capture

tests/test_logic_sim.py

@@ -75,9 +75,9 @@ def test_8v():
 
 def test_loop():
     c = bench.parse('q=dff(d) d=not(q)')
-    s = LogicSim(c, 2, m=8)
+    s = LogicSim(c, 4, m=8)
     assert len(s.interface) == 1
-    mva = MVArray([['0'], ['1']], m=8)
+    mva = MVArray([['0'], ['1'], ['R'], ['F']], m=8)
 
     s.assign(BPArray(mva))
     s.propagate()
@@ -85,14 +85,18 @@ def test_loop():
     s.capture(resp_bp)
     resp = MVArray(resp_bp)
 
-    assert resp[0] == 'R'
-    assert resp[1] == 'F'
+    assert resp[0] == '1'
+    assert resp[1] == '0'
+    assert resp[2] == 'F'
+    assert resp[3] == 'R'
 
     resp_bp = s.cycle(resp_bp)
     resp = MVArray(resp_bp)
 
-    assert resp[0] == 'F'
-    assert resp[1] == 'R'
+    assert resp[0] == '0'
+    assert resp[1] == '1'
+    assert resp[2] == 'R'
+    assert resp[3] == 'F'
 
 
 def test_latch():

tests/test_stil.py

@@ -13,9 +13,9 @@ def test_b14(mydir):
     assert len(tests) > 0
     assert len(resp) > 0
     
-    #s2 = stil.load(mydir / 'b14.transition.stil.gz')
-    #tests = s2.tests_loc(b14)
-    #resp = s2.responses(b14)
-    #assert len(tests) > 0
-    #assert len(resp) > 0
+    s2 = stil.load(mydir / 'b14.transition.stil.gz')
+    tests = s2.tests_loc(b14)
+    resp = s2.responses(b14)
+    assert len(tests) > 0
+    assert len(resp) > 0