first gpu-code, cached test fixtures

tests/conftest.py

@@ -1,8 +1,18 @@
 import pytest
 
 
-@pytest.fixture
+@pytest.fixture(scope='session')
 def mydir():
     import os
     from pathlib import Path
     return Path(os.path.realpath(os.path.join(os.getcwd(), os.path.dirname(__file__))))
+
+@pytest.fixture(scope='session')
+def b14_circuit(mydir):
+    from kyupy import verilog
+    return verilog.load(mydir / 'b14.v.gz', branchforks=True)
+
+@pytest.fixture(scope='session')
+def b14_timing(mydir, b14_circuit):
+    from kyupy import sdf
+    return sdf.load(mydir / 'b14.sdf.gz').annotation(b14_circuit)

tests/test_wave_sim4.py

@@ -1,6 +1,6 @@
 import numpy as np
 
-from kyupy.wave_sim4 import WaveSim, wave_eval, TMIN, TMAX
+from kyupy.wave_sim4 import WaveSim, WaveSimCuda, wave_eval_cpu, TMIN, TMAX
 from kyupy.logic_sim import LogicSim
 from kyupy import verilog, sdf, logic, bench
 from kyupy.logic import MVArray, BPArray
@@ -32,7 +32,7 @@ def test_nand_delays():
 
     def wave_assert(inputs, output):
         for i, a in zip(inputs, c.reshape(-1,16)): a[:len(i)] = i
-        wave_eval(op, c, vat, 0, line_times, sdata)
+        wave_eval_cpu(op, c, vat, 0, line_times, sdata)
         for i, v in enumerate(output): np.testing.assert_allclose(c.reshape(-1,16)[4,i], v)
 
     wave_assert([[TMAX,TMAX],[TMAX,TMAX],[TMIN,TMAX],[TMIN,TMAX]], [TMIN,TMAX]) # NAND(0,0,1,1) => 1
@@ -53,7 +53,6 @@ def test_tiny_circuit():
     lt = np.zeros((len(c.lines), 2, 2))
     lt[:,0,:] = 1.0  # unit delay for all lines
     wsim = WaveSim(c, lt)
-    print(wsim.prim_counts)
     assert len(wsim.s) == 5
     
     # values for x
@@ -157,18 +156,11 @@ def compare_to_logic_sim(wsim: WaveSim):
         assert res_str == exp_str
 
 
-def test_b14(mydir):
-    c = verilog.load(mydir / 'b14.v.gz', branchforks=True)
-    df = sdf.load(mydir / 'b14.sdf.gz')
-    lt = df.annotation(c)
-    wsim = WaveSim(c, lt, 8)
-    compare_to_logic_sim(wsim)
+def test_b14(b14_circuit, b14_timing):
+    compare_to_logic_sim(WaveSim(b14_circuit, b14_timing, 8))
 
+def test_b14_strip_forks(b14_circuit, b14_timing):
+    compare_to_logic_sim(WaveSim(b14_circuit, b14_timing, 8, strip_forks=True))
 
-def test_b14_strip_forks(mydir):
-    c = verilog.load(mydir / 'b14.v.gz', branchforks=True)
-    df = sdf.load(mydir / 'b14.sdf.gz')
-    lt = df.annotation(c)
-    wsim = WaveSim(c, lt, 8, strip_forks=True)
-    compare_to_logic_sim(wsim)
-
+def test_b14_cuda(b14_circuit, b14_timing):
+    compare_to_logic_sim(WaveSimCuda(b14_circuit, b14_timing, 8, strip_forks=True))