stefan
/
kyupy
2
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
A python module for parsing, processing, and simulating gate-level circuits.
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
150 Commits
2 Branches
4 Tags
60 MiB
 
 
 
Tree: 967a232b1c
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '967a232b1c'
${ noResults }
kyupy/tests
Stefan Holst 967a232b1c
fix pulse threshold selection 		1 year ago
..
__init__.py Project Import 4 years ago
b01.bench Project Import 4 years ago
b01.v Project Import 4 years ago
b15_2ig.sa_nf.stil.gz new into demo 1 year ago
b15_2ig.sdf.gz new into demo 1 year ago
b15_2ig.tf_nf.stil.gz new into demo 1 year ago
b15_2ig.v.gz doc improvements 1 year ago
b15_4ig.sdf.gz doc improvements 1 year ago
b15_4ig.v.gz doc improvements 1 year ago
conftest.py better docs, new techlib as default, fix tests 1 year ago
gates.sdf Project Import 4 years ago
gates.v Project Import 4 years ago
rng_haltonBase2.synth_yosys.v better docs, new techlib as default, fix tests 1 year ago
test_bench.py interface -> io_nodes, io_loc fix 2 years ago
test_circuit.py fix test 1 year ago
test_logic.py support more cells in logic sim 1 year ago
test_logic_sim.py fix simprim cells, add saed90 1 year ago
test_sdf.py better docs, new techlib as default, fix tests 1 year ago
test_stil.py better docs, new techlib as default, fix tests 1 year ago
test_verilog.py better docs, new techlib as default, fix tests 1 year ago
test_wave_sim.py fix pulse threshold selection 1 year ago