circuit node substitution

tests/test_circuit.py

@@ -1,7 +1,8 @@
 import pickle
 
 from kyupy.circuit import Circuit, Node, Line
-from kyupy import verilog
+from kyupy import verilog, bench
+from kyupy.techlib import TechLib
 
 def test_lines():
     c = Circuit()
@@ -104,9 +105,26 @@ def test_circuit():
 
 
 def test_pickle(mydir):
-    c = verilog.load(mydir / 'b14.v.gz')
+    c = verilog.load(mydir / 'b15_4ig.v.gz')
     assert c is not None
     cs = pickle.dumps(c)
     assert cs is not None
     c2 = pickle.loads(cs)
     assert c == c2
+
+def test_substitute():
+    c = bench.parse('input(i1, i2, i3, i4, i5) output(o1) aoi=AOI221(i1, i2, i3, i4, i5) o1=not(aoi)')
+    assert len(c.cells) == 2
+    assert len(c.io_nodes) == 6
+    aoi221_impl = bench.parse('input(in1, in2, in3, in4, in5) output(q) a1=and(in1, in2) a2=and(in3, in4) q=or(a1, a2, in5)')
+    assert len(aoi221_impl.cells) == 3
+    assert len(aoi221_impl.io_nodes) == 6
+    c.substitute(c.cells['aoi'], aoi221_impl)
+    assert len(c.cells) == 4
+    assert len(c.io_nodes) == 6
+
+    c = bench.parse('input(i1, i2, i3, i4, i5) output(o1) aoi221=AOI221(i1, i2, i3, i4, i5) o1=not(aoi221)')
+    assert len(c.cells) == 2
+    TechLib.substitute_nonsim_cells(c)
+    assert len(c.cells) == 3
+    print('\n'.join(map(str, c.nodes)))