preserve node order during resolve

src/kyupy/circuit.py

@@ -366,15 +366,19 @@ class Circuit:
         node_out_lines = list(node.outs) + [None] * (len(impl_out_lines)-len(node.outs))
         assert len(node_in_lines) == len(impl_in_lines)
         assert len(node_out_lines) == len(impl_out_lines)
-        node.remove()
         node_map = dict()
+        if designated_cell is not None:
+            node.kind = designated_cell.kind
+            node_map[designated_cell] = node
+        else:
+            node.remove()
         ios = set(impl.io_nodes)
         for n in impl.nodes:  # add all nodes to main circuit
             if n not in ios:
-                suffix = '' if n == designated_cell else f'~{n.name}'
-                node_map[n] = Node(self, node.name + suffix, n.kind)
+                if n != designated_cell:
+                    node_map[n] = Node(self, f'{node.name}~{n.name}', n.kind)
             elif len(n.outs) > 0 and len(n.ins) > 0:  # output is also read by impl. circuit, need to add a fork.
-                node_map[n] = Node(self, node.name + '~' + n.name)
+                node_map[n] = Node(self, f'{node.name}~{n.name}')
         for l in impl.lines:  # add all internal lines to main circuit
             if l.reader in node_map and l.driver in node_map:
                 Line(self, (node_map[l.driver], l.driver_pin), (node_map[l.reader], l.reader_pin))

tests/test_circuit.py

@@ -2,7 +2,7 @@ import pickle
 
 from kyupy.circuit import Circuit, Node, Line
 from kyupy import verilog, bench
-from kyupy.techlib import TechLib
+from kyupy.techlib import SAED32
 
 def test_lines():
     c = Circuit()
@@ -105,13 +105,14 @@ def test_circuit():
 
 
 def test_pickle(mydir):
-    c = verilog.load(mydir / 'b15_4ig.v.gz')
+    c = verilog.load(mydir / 'b15_4ig.v.gz', tlib=SAED32)
     assert c is not None
     cs = pickle.dumps(c)
     assert cs is not None
     c2 = pickle.loads(cs)
     assert c == c2
 
+
 def test_substitute():
     c = bench.parse('input(i1, i2, i3, i4, i5) output(o1) aoi=AOI221(i1, i2, i3, i4, i5) o1=not(aoi)')
     assert len(c.cells) == 2
@@ -123,8 +124,10 @@ def test_substitute():
     assert len(c.cells) == 4
     assert len(c.io_nodes) == 6
 
-    c = bench.parse('input(i1, i2, i3, i4, i5) output(o1) aoi221=AOI221(i1, i2, i3, i4, i5) o1=not(aoi221)')
-    assert len(c.cells) == 2
-    TechLib.substitute_nonsim_cells(c)
-    assert len(c.cells) == 3
-    print('\n'.join(map(str, c.nodes)))
+
+def test_resolve(mydir):
+    c = verilog.load(mydir / 'b15_4ig.v.gz', tlib=SAED32)
+    s_names = [n.name for n in c.s_nodes]
+    c.resolve_tlib_cells(SAED32)
+    s_names_prim = [n.name for n in c.s_nodes]
+    assert s_names == s_names_prim, 'resolve_tlib_cells does not preserve names or order of s_nodes'