fix sim model generation for circuits with dangling nodes

tests/test_logic_sim.py

@@ -3,6 +3,22 @@ import numpy as np
 from kyupy.logic_sim import LogicSim, LogicSim2V, LogicSim4V, LogicSim6V
 from kyupy import bench, logic, sim, verilog
 from kyupy.logic import mvarray, bparray, bp_to_mv, mv_to_bp
+from kyupy.techlib import SAED90
+
+def test_dangling():
+    c = verilog.parse('''
+        module test(i, o);
+            input i; output o; wire dangling;
+            INVX0 dff1 (.INP(i),.ZN(o));
+            assign dangling=o;
+        endmodule
+    ''', tlib=SAED90)
+    c.resolve_tlib_cells(SAED90)
+    sim = LogicSim2V(c)
+    p = sim.allocate()
+    p[...] = 0
+    sim.simulate(p)
+    assert p[1,0] == logic.ONE
 
 def assert_equal_shape_and_contents(actual, desired):
     desired = np.array(desired, dtype=np.uint8)