Stefan Holst 864230b883 initial letch support, fix capture in logic sim

2021-03-25 10:36:55 +09:00

..

__init__.py

Project Import

2020-10-29 16:45:33 +09:00

b01.bench

Project Import

2020-10-29 16:45:33 +09:00

b01.v

Project Import

2020-10-29 16:45:33 +09:00

b14.sdf.gz

updated b14 benchmark, update wavesim capture api, expand usage examples

2020-11-29 22:32:47 +09:00

b14.stuck.stil.gz

updated b14 benchmark, update wavesim capture api, expand usage examples

2020-11-29 22:32:47 +09:00

b14.transition.stil.gz

updated b14 benchmark, update wavesim capture api, expand usage examples

2020-11-29 22:32:47 +09:00

b14.v.gz

updated b14 benchmark, update wavesim capture api, expand usage examples

2020-11-29 22:32:47 +09:00

conftest.py

Project Import

2020-10-29 16:45:33 +09:00

gates.sdf

Project Import

2020-10-29 16:45:33 +09:00

gates.v

Project Import

2020-10-29 16:45:33 +09:00

test_bench.py

de-lint and repr improvements

2021-01-12 15:32:18 +09:00

test_circuit.py

Documenting circuit module

2020-12-18 21:14:00 +09:00

test_logic_sim.py

initial letch support, fix capture in logic sim

2021-03-25 10:36:55 +09:00

test_logic.py

initial letch support, fix capture in logic sim

2021-03-25 10:36:55 +09:00

test_sdf.py

TechLib class, remove unnecessary .index

2021-01-16 13:17:18 +09:00

test_stil.py

de-lint and repr improvements

2021-01-12 15:32:18 +09:00

test_verilog.py

Documentation, cleanup, multi-valued logic

2020-12-20 17:44:04 +09:00

test_wave_sim.py

TechLib class, remove unnecessary .index

2021-01-16 13:17:18 +09:00