preserve node order during resolve

tests/test_circuit.py

@@ -2,7 +2,7 @@ import pickle
 
 from kyupy.circuit import Circuit, Node, Line
 from kyupy import verilog, bench
-from kyupy.techlib import TechLib
+from kyupy.techlib import SAED32
 
 def test_lines():
     c = Circuit()
@@ -105,13 +105,14 @@ def test_circuit():
 
 
 def test_pickle(mydir):
-    c = verilog.load(mydir / 'b15_4ig.v.gz')
+    c = verilog.load(mydir / 'b15_4ig.v.gz', tlib=SAED32)
     assert c is not None
     cs = pickle.dumps(c)
     assert cs is not None
     c2 = pickle.loads(cs)
     assert c == c2
 
+
 def test_substitute():
     c = bench.parse('input(i1, i2, i3, i4, i5) output(o1) aoi=AOI221(i1, i2, i3, i4, i5) o1=not(aoi)')
     assert len(c.cells) == 2
@@ -123,8 +124,10 @@ def test_substitute():
     assert len(c.cells) == 4
     assert len(c.io_nodes) == 6
 
-    c = bench.parse('input(i1, i2, i3, i4, i5) output(o1) aoi221=AOI221(i1, i2, i3, i4, i5) o1=not(aoi221)')
-    assert len(c.cells) == 2
-    TechLib.substitute_nonsim_cells(c)
-    assert len(c.cells) == 3
-    print('\n'.join(map(str, c.nodes)))
+
+def test_resolve(mydir):
+    c = verilog.load(mydir / 'b15_4ig.v.gz', tlib=SAED32)
+    s_names = [n.name for n in c.s_nodes]
+    c.resolve_tlib_cells(SAED32)
+    s_names_prim = [n.name for n in c.s_nodes]
+    assert s_names == s_names_prim, 'resolve_tlib_cells does not preserve names or order of s_nodes'