alap toposort, improve tests

tests/conftest.py

@@ -13,6 +13,13 @@ def b15_2ig_circuit(mydir):
     from kyupy.techlib import SAED32
     return verilog.load(mydir / 'b15_2ig.v.gz', branchforks=True, tlib=SAED32)
 
+@pytest.fixture(scope='session')
+def b15_2ig_circuit_resolved(b15_2ig_circuit):
+    from kyupy.techlib import SAED32
+    cr = b15_2ig_circuit.copy()
+    cr.resolve_tlib_cells(SAED32)
+    return cr
+
 @pytest.fixture(scope='session')
 def b15_2ig_delays(mydir, b15_2ig_circuit):
     from kyupy import sdf

tests/test_logic_sim.py

@@ -173,3 +173,50 @@ def test_b01(mydir):
     s.c_prop()
     s.c_to_s()
     bp_to_mv(s.s[1])
+
+
+def sim_and_compare(v_file, stil_file, m=8):
+    from kyupy import verilog, stil
+    from kyupy.techlib import SAED32
+    c = verilog.load(v_file, branchforks=True, tlib=SAED32)
+    c.resolve_tlib_cells(SAED32)
+    s = stil.load(stil_file)
+    tests = s.tests(c)[:,1:]
+    resp = s.responses(c)[:,1:]
+    lsim = LogicSim(c, m=m, sims=tests.shape[1])
+    lsim.s[0] = logic.mv_to_bp(tests)
+    lsim.s_to_c()
+    lsim.c_prop()
+    lsim.c_to_s()
+    resp_sim = logic.bp_to_mv(lsim.s[1])[:,:tests.shape[1]]
+    idxs, pats = np.nonzero(((resp == logic.ONE) & (resp_sim != logic.ONE)) | ((resp == logic.ZERO) & (resp_sim != logic.ZERO)))
+    for i, (idx, pat) in enumerate(zip(idxs, pats)):
+        if i >= 10:
+            print(f'...')
+            break
+        print(f'mismatch pattern:{pat} ppio:{idx} exp:{logic.mv_str(resp[idx,pat])} act:{logic.mv_str(resp_sim[idx,pat])}')
+    assert len(idxs) == 0
+
+
+def test_b15_2ig_sa_2v(mydir):
+    sim_and_compare(mydir / 'b15_2ig.v.gz', mydir / 'b15_2ig.sa_nf.stil.gz', m=2)
+
+
+def test_b15_2ig_sa_4v(mydir):
+    sim_and_compare(mydir / 'b15_2ig.v.gz', mydir / 'b15_2ig.sa_nf.stil.gz', m=4)
+
+
+def test_b15_2ig_sa_8v(mydir):
+    sim_and_compare(mydir / 'b15_2ig.v.gz', mydir / 'b15_2ig.sa_nf.stil.gz', m=8)
+
+
+def test_b15_4ig_sa_2v(mydir):
+    sim_and_compare(mydir / 'b15_4ig.v.gz', mydir / 'b15_4ig.sa_rf.stil.gz', m=2)
+
+
+def test_b15_4ig_sa_4v(mydir):
+    sim_and_compare(mydir / 'b15_4ig.v.gz', mydir / 'b15_4ig.sa_rf.stil.gz', m=4)
+
+
+def test_b15_4ig_sa_8v(mydir):
+    sim_and_compare(mydir / 'b15_4ig.v.gz', mydir / 'b15_4ig.sa_rf.stil.gz', m=8)

tests/test_wave_sim.py

@@ -177,7 +177,7 @@ def compare_to_logic_sim(wsim: WaveSim):
     lsim.s_to_c()
     lsim.c_prop()
     lsim.c_to_s()
-    exp = logic.bp_to_mv(lsim.s[1])
+    exp = logic.bp_to_mv(lsim.s[1])[:,:tests.shape[-1]]
 
     resp[resp == logic.PPULSE] = logic.ZERO
     resp[resp == logic.NPULSE] = logic.ONE
@@ -188,13 +188,13 @@ def compare_to_logic_sim(wsim: WaveSim):
     np.testing.assert_allclose(resp, exp)
 
 
-def test_b15(b15_2ig_circuit, b15_2ig_delays):
-    compare_to_logic_sim(WaveSim(b15_2ig_circuit, b15_2ig_delays, 8))
+def test_b15(b15_2ig_circuit_resolved, b15_2ig_delays):
+    compare_to_logic_sim(WaveSim(b15_2ig_circuit_resolved, b15_2ig_delays, 8))
 
 
-def test_b15_strip_forks(b15_2ig_circuit, b15_2ig_delays):
-    compare_to_logic_sim(WaveSim(b15_2ig_circuit, b15_2ig_delays, 8, strip_forks=True))
+def test_b15_strip_forks(b15_2ig_circuit_resolved, b15_2ig_delays):
+    compare_to_logic_sim(WaveSim(b15_2ig_circuit_resolved, b15_2ig_delays, 8, strip_forks=True))
 
 
-def test_b15_cuda(b15_2ig_circuit, b15_2ig_delays):
-    compare_to_logic_sim(WaveSimCuda(b15_2ig_circuit, b15_2ig_delays, 8, strip_forks=True))
+def test_b15_cuda(b15_2ig_circuit_resolved, b15_2ig_delays):
+    compare_to_logic_sim(WaveSimCuda(b15_2ig_circuit_resolved, b15_2ig_delays, 8, strip_forks=True))