better docs, new techlib as default, fix tests
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Stefan Holst committed
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83445e2bbd
commit
35e727e714
20 files changed
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-262
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+4
-4
@@ -8,13 +8,13 @@ def mydir():
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return Path(os.path.realpath(os.path.join(os.getcwd(), os.path.dirname(__file__))))
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@pytest.fixture(scope='session')
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def b14_circuit(mydir):
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def b15_2ig_circuit(mydir):
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from kyupy import verilog
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from kyupy.techlib import SAED32
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return verilog.load(mydir / 'b14.v.gz', branchforks=True, tlib=SAED32)
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return verilog.load(mydir / 'b15_2ig.v.gz', branchforks=True, tlib=SAED32)
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@pytest.fixture(scope='session')
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def b14_delays(mydir, b14_circuit):
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def b15_2ig_delays(mydir, b15_2ig_circuit):
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from kyupy import sdf
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from kyupy.techlib import SAED32
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return sdf.load(mydir / 'b14.sdf.gz').iopaths(b14_circuit, tlib=SAED32)[1:2]
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return sdf.load(mydir / 'b15_2ig.sdf.gz').iopaths(b15_2ig_circuit, tlib=SAED32)[1:2]
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@@ -0,0 +1,335 @@
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/* Generated by Yosys 0.9 (git sha1 UNKNOWN, gcc 4.8.5 -fPIC -Os) */
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(* top = 1 *)
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(* src = "rng_haltonBase2.v:1" *)
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module rng1(clk, reset, o_output);
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:19" *)
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wire [11:0] _00_;
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wire _01_;
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wire _02_;
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wire _03_;
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wire _04_;
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wire _05_;
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wire _06_;
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wire _07_;
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wire _08_;
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wire _09_;
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wire _10_;
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wire _11_;
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wire _12_;
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wire _13_;
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wire _14_;
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wire _15_;
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wire _16_;
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wire _17_;
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wire _18_;
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wire _19_;
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wire _20_;
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wire _21_;
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wire _22_;
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wire _23_;
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wire _24_;
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wire _25_;
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wire _26_;
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wire _27_;
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wire _28_;
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wire _29_;
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wire _30_;
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wire _31_;
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wire _32_;
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wire _33_;
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wire _34_;
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(* src = "rng_haltonBase2.v:2" *)
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input clk;
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:12" *)
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wire \halton.clk ;
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(* init = 12'h000 *)
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:17" *)
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wire [11:0] \halton.counter ;
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:14" *)
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wire [11:0] \halton.o_output ;
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:13" *)
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wire \halton.reset ;
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(* src = "rng_haltonBase2.v:4" *)
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output [11:0] o_output;
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(* src = "rng_haltonBase2.v:3" *)
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input reset;
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AND2X1 _35_ (
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.IN1(\halton.counter [1]),
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.IN2(\halton.counter [0]),
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.Q(_01_)
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);
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NOR2X0 _36_ (
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.IN1(\halton.counter [1]),
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.IN2(\halton.counter [0]),
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.QN(_02_)
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);
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NOR3X0 _37_ (
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.IN1(reset),
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.IN2(_01_),
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.IN3(_02_),
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.QN(_00_[1])
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);
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AND2X1 _38_ (
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.IN1(\halton.counter [2]),
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.IN2(_01_),
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.Q(_03_)
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);
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NOR2X0 _39_ (
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.IN1(\halton.counter [2]),
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.IN2(_01_),
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.QN(_04_)
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);
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NOR3X0 _40_ (
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.IN1(reset),
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.IN2(_03_),
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.IN3(_04_),
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.QN(_00_[2])
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);
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AND4X1 _41_ (
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.IN1(\halton.counter [1]),
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.IN2(\halton.counter [0]),
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.IN3(\halton.counter [2]),
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.IN4(\halton.counter [3]),
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.Q(_05_)
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);
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NOR2X0 _42_ (
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.IN1(\halton.counter [3]),
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.IN2(_03_),
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.QN(_06_)
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);
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NOR3X0 _43_ (
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.IN1(reset),
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.IN2(_05_),
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.IN3(_06_),
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.QN(_00_[3])
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);
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AND2X1 _44_ (
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.IN1(\halton.counter [4]),
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.IN2(_05_),
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.Q(_07_)
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);
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NOR2X0 _45_ (
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.IN1(\halton.counter [4]),
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.IN2(_05_),
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.QN(_08_)
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);
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NOR3X0 _46_ (
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.IN1(reset),
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.IN2(_07_),
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.IN3(_08_),
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.QN(_00_[4])
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);
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AND2X1 _47_ (
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.IN1(\halton.counter [5]),
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.IN2(_07_),
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.Q(_09_)
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);
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NOR2X0 _48_ (
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.IN1(\halton.counter [5]),
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.IN2(_07_),
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.QN(_10_)
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);
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NOR3X0 _49_ (
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.IN1(reset),
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.IN2(_09_),
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.IN3(_10_),
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.QN(_00_[5])
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);
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AND4X1 _50_ (
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.IN1(\halton.counter [4]),
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.IN2(\halton.counter [5]),
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.IN3(\halton.counter [6]),
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.IN4(_05_),
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.Q(_11_)
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);
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NOR2X0 _51_ (
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.IN1(\halton.counter [6]),
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.IN2(_09_),
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.QN(_12_)
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);
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NOR3X0 _52_ (
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.IN1(reset),
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.IN2(_11_),
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.IN3(_12_),
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.QN(_00_[6])
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);
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AND2X1 _53_ (
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.IN1(\halton.counter [7]),
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.IN2(_11_),
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.Q(_13_)
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);
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NOR2X0 _54_ (
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.IN1(\halton.counter [7]),
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.IN2(_11_),
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.QN(_14_)
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);
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NOR3X0 _55_ (
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.IN1(reset),
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.IN2(_13_),
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.IN3(_14_),
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.QN(_00_[7])
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);
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AND3X1 _56_ (
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.IN1(\halton.counter [7]),
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.IN2(\halton.counter [8]),
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.IN3(_11_),
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.Q(_15_)
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);
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NOR2X0 _57_ (
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.IN1(\halton.counter [8]),
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.IN2(_13_),
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.QN(_16_)
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);
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NOR3X0 _58_ (
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.IN1(reset),
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.IN2(_15_),
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.IN3(_16_),
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.QN(_00_[8])
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);
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AND4X1 _59_ (
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.IN1(\halton.counter [7]),
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.IN2(\halton.counter [8]),
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.IN3(\halton.counter [9]),
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.IN4(_11_),
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.Q(_17_)
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);
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NOR2X0 _60_ (
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.IN1(\halton.counter [9]),
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.IN2(_15_),
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.QN(_18_)
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);
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NOR3X0 _61_ (
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.IN1(reset),
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.IN2(_17_),
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.IN3(_18_),
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.QN(_00_[9])
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);
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AND2X1 _62_ (
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.IN1(\halton.counter [10]),
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.IN2(_17_),
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.Q(_19_)
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);
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NOR2X0 _63_ (
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.IN1(\halton.counter [10]),
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.IN2(_17_),
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.QN(_20_)
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);
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NOR3X0 _64_ (
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.IN1(reset),
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.IN2(_19_),
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.IN3(_20_),
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.QN(_00_[10])
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);
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AND3X1 _65_ (
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.IN1(\halton.counter [10]),
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.IN2(\halton.counter [11]),
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.IN3(_17_),
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.Q(_21_)
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);
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AOI21X1 _66_ (
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.IN1(\halton.counter [10]),
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.IN2(_17_),
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.IN3(\halton.counter [11]),
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.QN(_22_)
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);
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NOR3X0 _67_ (
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.IN1(reset),
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.IN2(_21_),
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.IN3(_22_),
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.QN(_00_[11])
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);
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NOR2X0 _68_ (
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.IN1(reset),
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.IN2(\halton.counter [0]),
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.QN(_00_[0])
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);
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:19" *)
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DFFX1 _69_ (
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.CLK(clk),
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.D(_00_[0]),
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.Q(\halton.counter [0]),
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.QN(_23_)
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);
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:19" *)
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DFFX1 _70_ (
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.CLK(clk),
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.D(_00_[1]),
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.Q(\halton.counter [1]),
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.QN(_24_)
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);
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:19" *)
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DFFX1 _71_ (
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.CLK(clk),
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.D(_00_[2]),
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.Q(\halton.counter [2]),
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.QN(_25_)
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);
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:19" *)
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DFFX1 _72_ (
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.CLK(clk),
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.D(_00_[3]),
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.Q(\halton.counter [3]),
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.QN(_26_)
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);
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:19" *)
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DFFX1 _73_ (
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.CLK(clk),
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.D(_00_[4]),
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.Q(\halton.counter [4]),
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.QN(_27_)
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);
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:19" *)
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DFFX1 _74_ (
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.CLK(clk),
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.D(_00_[5]),
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.Q(\halton.counter [5]),
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.QN(_28_)
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);
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:19" *)
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DFFX1 _75_ (
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.CLK(clk),
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.D(_00_[6]),
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.Q(\halton.counter [6]),
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.QN(_29_)
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);
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:19" *)
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DFFX1 _76_ (
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.CLK(clk),
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.D(_00_[7]),
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.Q(\halton.counter [7]),
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.QN(_30_)
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);
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:19" *)
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DFFX1 _77_ (
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.CLK(clk),
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.D(_00_[8]),
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.Q(\halton.counter [8]),
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.QN(_31_)
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);
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:19" *)
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DFFX1 _78_ (
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.CLK(clk),
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.D(_00_[9]),
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.Q(\halton.counter [9]),
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.QN(_32_)
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);
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:19" *)
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DFFX1 _79_ (
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.CLK(clk),
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.D(_00_[10]),
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.Q(\halton.counter [10]),
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.QN(_33_)
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);
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(* src = "rng_haltonBase2.v:7|rng_haltonBase2.v:19" *)
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DFFX1 _80_ (
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.CLK(clk),
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.D(_00_[11]),
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.Q(\halton.counter [11]),
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.QN(_34_)
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);
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assign \halton.clk = clk;
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assign \halton.o_output = { \halton.counter [0], \halton.counter [1], \halton.counter [2], \halton.counter [3], \halton.counter [4], \halton.counter [5], \halton.counter [6], \halton.counter [7], \halton.counter [8], \halton.counter [9], \halton.counter [10], \halton.counter [11] };
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assign \halton.reset = reset;
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assign o_output = { \halton.counter [0], \halton.counter [1], \halton.counter [2], \halton.counter [3], \halton.counter [4], \halton.counter [5], \halton.counter [6], \halton.counter [7], \halton.counter [8], \halton.counter [9], \halton.counter [10], \halton.counter [11] };
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endmodule
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+3
-4
@@ -72,12 +72,11 @@ def test_parse():
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'''
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df = sdf.parse(test)
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assert df.name == 'test'
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# print(f'DelayFile(name={df.name}, interconnects={len(df.interconnects)}, iopaths={len(df.iopaths)})')
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def test_b14(mydir):
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df = sdf.load(mydir / 'b14.sdf.gz')
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assert df.name == 'b14'
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def test_b15(mydir):
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df = sdf.load(mydir / 'b15_2ig.sdf.gz')
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assert df.name == 'b15'
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def test_gates(mydir):
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+10
-10
@@ -1,21 +1,21 @@
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from kyupy import stil, verilog
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from kyupy.techlib import SAED32
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def test_b15(mydir):
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b15 = verilog.load(mydir / 'b15_2ig.v.gz', tlib=SAED32)
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def test_b14(mydir):
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b14 = verilog.load(mydir / 'b14.v.gz')
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s = stil.load(mydir / 'b14.stuck.stil.gz')
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s = stil.load(mydir / 'b15_2ig.sa_nf.stil.gz')
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assert len(s.signal_groups) == 10
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assert len(s.scan_chains) == 1
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assert len(s.calls) == 2163
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tests = s.tests(b14)
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resp = s.responses(b14)
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assert len(s.calls) == 1357
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tests = s.tests(b15)
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resp = s.responses(b15)
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assert len(tests) > 0
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assert len(resp) > 0
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|
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s2 = stil.load(mydir / 'b14.transition.stil.gz')
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tests = s2.tests_loc(b14)
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resp = s2.responses(b14)
|
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s2 = stil.load(mydir / 'b15_2ig.tf_nf.stil.gz')
|
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tests = s2.tests_loc(b15)
|
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resp = s2.responses(b15)
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assert len(tests) > 0
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assert len(resp) > 0
|
||||
|
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@@ -1,11 +1,11 @@
|
||||
from kyupy import verilog
|
||||
|
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from kyupy.techlib import SAED90, SAED32
|
||||
|
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def test_b01(mydir):
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with open(mydir / 'b01.v', 'r') as f:
|
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c = verilog.parse(f.read())
|
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c = verilog.parse(f.read(), tlib=SAED90)
|
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assert c is not None
|
||||
assert verilog.load(mydir / 'b01.v') is not None
|
||||
assert verilog.load(mydir / 'b01.v', tlib=SAED90) is not None
|
||||
|
||||
assert len(c.nodes) == 139
|
||||
assert len(c.lines) == 203
|
||||
@@ -16,7 +16,7 @@ def test_b01(mydir):
|
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|
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|
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def test_b15(mydir):
|
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c = verilog.load(mydir / 'b15_4ig.v.gz')
|
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c = verilog.load(mydir / 'b15_4ig.v.gz', tlib=SAED32)
|
||||
assert len(c.nodes) == 12067
|
||||
assert len(c.lines) == 20731
|
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stats = c.stats
|
||||
@@ -26,7 +26,7 @@ def test_b15(mydir):
|
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|
||||
|
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def test_gates(mydir):
|
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c = verilog.load(mydir / 'gates.v')
|
||||
c = verilog.load(mydir / 'gates.v', tlib=SAED90)
|
||||
assert len(c.nodes) == 10
|
||||
assert len(c.lines) == 10
|
||||
stats = c.stats
|
||||
@@ -36,7 +36,7 @@ def test_gates(mydir):
|
||||
|
||||
|
||||
def test_halton2(mydir):
|
||||
c = verilog.load(mydir / 'rng_haltonBase2.synth_yosys.v')
|
||||
c = verilog.load(mydir / 'rng_haltonBase2.synth_yosys.v', tlib=SAED90)
|
||||
assert len(c.nodes) == 146
|
||||
assert len(c.lines) == 210
|
||||
stats = c.stats
|
||||
|
||||
@@ -156,16 +156,13 @@ def compare_to_logic_sim(wsim: WaveSim):
|
||||
np.testing.assert_allclose(resp, exp)
|
||||
|
||||
|
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def test_b14(b14_circuit, b14_delays):
|
||||
compare_to_logic_sim(WaveSim(b14_circuit, b14_delays, 8))
|
||||
def test_b15(b15_2ig_circuit, b15_2ig_delays):
|
||||
compare_to_logic_sim(WaveSim(b15_2ig_circuit, b15_2ig_delays, 8))
|
||||
|
||||
|
||||
def test_b14_strip_forks(b14_circuit, b14_delays):
|
||||
compare_to_logic_sim(WaveSim(b14_circuit, b14_delays, 8, strip_forks=True))
|
||||
def test_b15_strip_forks(b15_2ig_circuit, b15_2ig_delays):
|
||||
compare_to_logic_sim(WaveSim(b15_2ig_circuit, b15_2ig_delays, 8, strip_forks=True))
|
||||
|
||||
|
||||
def test_b14_cuda(b14_circuit, b14_delays):
|
||||
compare_to_logic_sim(WaveSimCuda(b14_circuit, b14_delays, 8, strip_forks=True))
|
||||
|
||||
if __name__ == '__main__':
|
||||
test_nand_delays()
|
||||
def test_b15_cuda(b15_2ig_circuit, b15_2ig_delays):
|
||||
compare_to_logic_sim(WaveSimCuda(b15_2ig_circuit, b15_2ig_delays, 8, strip_forks=True))
|
||||
Reference in new issue
Block a user