191 Commits
Author SHA1 Message Date
stefan c4aecbd6c9 skywater 130nm tech library 2026-04-26 22:17:03 +09:00
stefan 25ff1fb2dc fixups for empty standard cells 2026-04-26 22:16:32 +09:00
stefan f0b55eed27 version bump 2025-11-27 22:01:32 +09:00
stefan 3700ae9b33 need 3.12 for generic types 2025-11-27 21:59:06 +09:00
stefan df695e0aa1 for release 0.0.6
- sim: added LogicSim2V, LogicSim4V, LogicSim6V (faster and simpler API)
- sim: fixed model for: many-input gates in bench; dangling nodes; POs that drive further logic
- Circuit: dot output fix and better style, fixed equivalence check of lines and nodes.
- Techlib: Added KYUPY library with supported simulation primitives for debug and testing
- tests: fixed and added more for better coverage
- more type annotations
- updated project config and dependencies for better uv experience, newer lark, newer numpy
2025-11-27 21:59:06 +09:00
stefan a28128830d beginning simple always block parsing in verilog 2025-11-27 21:19:59 +09:00
stefan 20cf441abb add doc gen dependencies 2025-11-23 22:48:16 +09:00
stefan 5ac21edbb1 migrate readme to markdown 2025-11-23 22:39:31 +09:00
stefan f0d74777af add dff to techlib 2025-11-23 21:35:49 +09:00
stefan 3848665533 ignore more generated python files 2025-11-23 21:35:30 +09:00
stefan 541cccd756 fix sim model for PO that also drive further logic 2025-11-23 21:34:58 +09:00
stefan fed66f85cb fix oob in test 2025-11-23 21:31:56 +09:00
stefan 2eb10f83b0 add pytest dev dependency 2025-11-23 21:31:40 +09:00
stefan dd4e5c861a fix sim model generation for circuits with dangling nodes 2025-11-20 15:28:41 +09:00
stefan 9cebbcce8f support for storing responses separately 2025-11-11 18:13:08 +09:00
stefan 31434cfd51 4v sim, fixed 6v sim, better testing 2025-11-09 08:09:46 +09:00
stefan ce94210b52 adding more types 2025-11-09 08:08:03 +09:00
stefan 09420fd72c new logic sim interface prototype, simprim lib and test 2025-11-02 20:56:14 +09:00
stefan 5bcc1c1d77 new synthetic techlib with kyupy simprims 2025-11-02 20:49:37 +09:00
stefan df8a58f57b generate proper simprims in bench parser 2025-11-02 20:44:04 +09:00
stefan 3dfd0cb60d euivalence test, op format doc 2025-10-31 17:13:58 +09:00
stefan 21439e3595 circuit objects and nodes/lines of different circuits are not quivalent. 2025-10-31 17:12:50 +09:00
stefan 88a5c79161 dot fix and updated intro nb 2025-10-23 22:48:18 +09:00
stefan 9ca437fe47 fault injection for 4v sim, wave_sim test fix 2025-10-23 21:26:52 +09:00
stefan 0cdaf71963 fix for latest lark 2025-10-23 21:25:50 +09:00
stefan 75972d7bb2 numba config deprecated 2025-10-23 21:25:36 +09:00
stefan 469dc18aa9 lark dependency update 2025-10-23 18:20:29 +09:00
stefan 33addab141 fix output with newest numpy 2025-10-22 14:17:44 +09:00
stefan 674f3dea4a Merge branch 'main' into devel 2025-06-23 16:06:02 +09:00
stefan 187d176cfd partial ternary if support 2025-06-02 12:20:42 +09:00
stefan ba1de0bea9 support for per-simulation delay factors 2025-01-17 13:17:44 +09:00
stefan 5769aa3716 deactivate delta sim 2025-01-17 11:28:12 +09:00
stefan e97c370d39 support stuck-at fault model injection for 2-valued logic sim 2024-12-06 13:42:22 +09:00
stefan 3b7106be80 fix deferred assignments 2024-11-07 17:06:00 +09:00
stefan d2357859f6 more robust matching and assign processing 2024-04-15 17:01:11 +09:00
stefan 53629c5c28 support injection into specific sims 2024-04-12 15:23:54 +09:00
stefan e64845e8c0 fanout generator 2024-04-10 19:28:32 +09:00
stefan da98ca2db7 signal flips in compiled code 2024-04-10 19:27:06 +09:00
stefan deb4599206 fix tests 2024-04-08 23:21:24 +09:00
stefan c1c9ec9aae pin_name, cleanup legacy code 2024-04-08 16:35:21 +09:00
stefan 4c55dcec60 delta sim for improving fault sim performance 2024-04-08 00:29:12 +09:00
stefan a4b7364478 mux21 in 6v logic sim, more test fixtures 2024-04-06 15:22:46 +09:00
stefan f59e97afa9 remove hashes, add lst, overflow, ebuf 2024-04-05 23:24:00 +09:00
stefan f6baf9cb5e a fast 6v sim 2024-04-05 23:21:59 +09:00
stefan fc030c6708 allow interconnect annotations without forks 2024-04-05 23:21:23 +09:00
Stefan Holst 795cac0716 initial and final values from mvarrays 2024-04-04 20:44:22 +09:00
Stefan Holst 3a8777e0a3 none-filtering iterator for GrowingList 2024-04-04 20:41:59 +09:00
Stefan Holst 68e8cb844a pass line id to inject_cb 2024-02-16 09:48:52 +09:00
stefan 1a3b91c1c0 fix comment 2023-12-06 16:45:34 +09:00
Stefan Holst aa7536b8b0 line use and diff 2023-12-06 16:44:17 +09:00
Stefan Holst fccf5e0d84 fix log limit 2023-12-06 16:43:42 +09:00
Stefan Holst a6d1e4099c alap toposort, improve tests 2023-11-07 12:44:19 +09:00
Stefan Holst 1654915ed6 support for partial re-sim 2023-11-03 14:26:48 +09:00
Stefan Holst d2a2484efa fix fault injection 2023-11-03 14:26:04 +09:00
Stefan Holst de79393dfc fix log limiter, use eng notation 2023-09-26 13:58:38 +09:00
Stefan Holst 4bb3f3424a cond in sdf parser. ignored for now. 2023-09-11 23:44:28 +09:00
Stefan Holst a6243b43f6 keep s_nodes 2023-09-11 23:41:51 +09:00
Stefan Holst baeb759824 types, perf op growing list, keep s_nodes 2023-08-07 21:59:08 +09:00
Stefan Holst 967a232b1c fix pulse threshold selection 2023-07-29 09:45:48 +09:00
Stefan Holst 8096416b0e save test position for each pattern 2023-07-28 17:26:28 +09:00
Stefan Holst a4cce9f8c0 Produce stable value when trans. to/from - 2023-07-28 17:20:34 +09:00
Stefan Holst 4f6b733eb4 fix NanGate variants, version bump 2023-07-26 17:18:28 +09:00
Stefan Holst 371bc906b3 Merge branch 'main' into devel
fix readthedocs
2023-07-22 17:09:46 +09:00
Stefan Holst 0ade89defa remove old test data, intro check 2023-07-22 15:58:16 +09:00
Stefan Holst 7f4026f504 def-file docs 2023-07-22 15:52:51 +09:00
Stefan Holst e6a0d59d44 def-file docs 2023-07-22 15:52:28 +09:00
Stefan Holst 63e5f32e21 better ignore 2023-07-22 13:24:25 +09:00
Stefan Holst 35e727e714 better docs, new techlib as default, fix tests 2023-07-22 13:11:11 +09:00
Stefan Holst 83445e2bbd support for newer NANGATE lib 2023-07-21 22:14:29 +09:00
Stefan Holst c67148c0ee doc fix 2023-07-21 22:13:25 +09:00
Stefan Holst 280c425486 fix test 2023-07-12 22:35:53 +09:00
Stefan Holst 5be82da49a avoid holes in forks, update intro 2023-07-12 22:32:22 +09:00
Stefan Holst b3dbe9765a fix xor in libs, remove old code 2023-07-12 21:10:27 +09:00
Stefan Holst 5e573b0408 fix substitute for inputs with fo, dot graph 2023-07-12 21:06:16 +09:00
Stefan Holst 08d9f5a9bf one-bit busses 2023-07-12 16:32:08 +09:00
Stefan Holst b098fb219d fix for unconnected named pins, double-declaration 2023-07-12 11:36:43 +09:00
Stefan Holst 97387e962b add GSC180nm 2023-07-12 11:35:15 +09:00
Stefan Holst f4d875f7e5 docs 2023-07-12 11:34:45 +09:00
Stefan Holst cf9a98b5ce del deprecated sdf code, explicit tlib use 2023-07-10 20:35:19 +09:00
Stefan Holst d8f605a47a fix double-free when fo goes to same cell 2023-07-10 20:08:48 +09:00
Stefan Holst ec5626b8ca remove old connections in substitute node reuse 2023-07-10 09:00:31 +09:00
Stefan Holst 5a693f7b9b preserve node order during resolve 2023-07-09 23:46:14 +09:00
Stefan Holst 19bbe2c260 update intro 2023-07-09 21:34:01 +09:00
Stefan Holst d3897246c5 move resolving cells to circuit, more doc 2023-07-09 19:04:22 +09:00
Stefan Holst 9bda7a4c57 capitalize tech libs 2023-07-09 19:01:31 +09:00
Stefan Holst 2270a9eee7 fix fork stripping + fork None values 2023-07-09 19:01:15 +09:00
Stefan Holst ea45a326ec add latch, fix xor delays, improve test 2023-07-09 13:42:07 +09:00
Stefan Holst 1e9fe7707b saed32nm 2023-07-09 00:29:56 +09:00
Stefan Holst 50a5d8a290 one cell inherits name in substitute, sim fix 2023-07-08 22:52:10 +09:00
Stefan Holst d97555e9e9 fix simprim cells, add saed90 2023-07-08 18:55:52 +09:00
Stefan Holst 47ee8d5878 improve substitute, update notebook output 2023-07-08 18:54:27 +09:00
Stefan Holst c32584fc76 1to1 fork optimization, fix substitute 2023-07-05 22:55:06 +09:00
Stefan Holst 39b8c1695b full constants support, fix signal declarations 2023-07-05 22:07:15 +09:00
Stefan Holst 80d26b6f0b Add AO*211 and OA*211, fix MUX21 2023-07-05 22:01:42 +09:00
Stefan Holst f7ef78e58d support for limiting log messages 2023-07-05 21:59:49 +09:00
Stefan Holst 7afb13b33b mv_str for single values, remove undue assert 2023-07-03 12:40:02 +09:00
Stefan Holst 153442a10a def file parser 2023-07-03 00:49:23 +09:00
Stefan Holst afb0a64953 wsa accumulation in wavesim 2023-07-03 00:48:58 +09:00
Stefan Holst c49667edc1 remove old code, verilog positional pins 2023-06-26 23:23:56 +09:00
Stefan Holst d921eb5048 sim support for remaining primitives 2023-06-25 22:27:19 +09:00
Stefan Holst 670fb0b3fc circuit node substitution 2023-06-25 22:26:52 +09:00
Stefan Holst f8bf579be2 support concat, bus select, ISOL cells 2023-06-24 23:41:08 +09:00
Stefan Holst f61e2b42e8 support more cells in logic sim 2023-06-24 13:34:35 +09:00
Stefan Holst 4aec335abb verilog: concat assignments, more comments 2023-06-24 13:33:55 +09:00
Stefan Holst 1a9cb396bf tweak repr, doc 2023-06-24 13:32:40 +09:00
Stefan Holst 3875dc38f9 docs 2023-06-21 23:23:01 +09:00
Stefan Holst ecb7171c37 docs 2023-06-21 23:18:17 +09:00
Stefan Holst 8957db48ab docs 2023-06-20 06:54:59 +09:00
Stefan Holst 0b15f9fa18 doc improvements 2023-06-19 17:05:39 +09:00
Stefan Holst dc76a9f517 new into demo 2023-06-19 14:01:31 +09:00
Stefan Holst 0968cb451e docs, fix stil unassigned, fix io_locs for busses 2023-06-19 13:12:17 +09:00
Stefan Holst 947df89434 add AOI21 to logic sim 2023-06-02 00:04:34 +09:00
Stefan Holst f17e461fdd fix reading directly from file handle 2023-05-19 14:57:02 +09:00
Stefan Holst d6d981a351 support for det vars 2023-04-05 18:35:55 +09:00
Stefan Holst 7a060b1831 support for static variations 2023-03-28 11:10:38 +09:00
Stefan Holst 03802ac9f8 make sims pickleable 2023-03-22 13:55:53 +09:00
Stefan Holst 70caea065e more cleanup 2023-03-20 14:14:06 +09:00
stefan f04f1b0012 cleanup 2023-03-20 10:31:55 +09:00
Stefan Holst 44b0c887d7 random sampling of delays 2023-03-19 20:30:27 +09:00
Stefan Holst 4e2022291e fix cuda ppo_to_ppi 2023-03-15 15:15:22 +09:00
Stefan Holst 5566b80e52 simprim, vat refactor, batchrange 2023-03-15 10:37:39 +09:00
stefan 63c0b48537 bump 2023-03-14 18:50:15 +09:00
stefan 6520ee23ef cleanup and new intro notebook 2023-03-14 17:40:50 +09:00
stefan 1810d40959 pytest work without cuda 2023-03-13 23:18:32 +09:00
Stefan Holst 7430ebb068 jitted logic sim 2023-03-13 23:15:20 +09:00
stefan 89f317b463 better circuit statsu, 2v logic sim 2023-03-13 10:50:44 +09:00
Stefan Holst 753ce566e4 Timer improvements, log in yaml 2023-03-13 10:45:41 +09:00
stefan 1eb8d87884 faster logic sim, removing MVArray, BPArray 2023-03-12 23:59:10 +09:00
stefan 02f3a0e1b2 correct timing padding 2023-02-28 09:39:01 +09:00
stefan fc8e65e788 bit-packing utility 2023-02-28 09:38:28 +09:00
stefan d80a3ae2b1 timer utility 2023-02-28 09:38:02 +09:00
Stefan Holst 7bfc02e683 more on-gpu code, bump python requirement 2023-02-26 22:37:15 +09:00
Stefan Holst 8da4a62bce switch to new wave_sim, silence occupancy warnings 2023-02-26 13:54:01 +09:00
stefan 3497bfdc75 first gpu-code, cached test fixtures 2023-02-26 13:09:49 +09:00
stefan f1ebe1487c new wave sim 2023-02-26 11:04:38 +09:00
stefan f0dac36ac7 interface -> io_nodes, io_loc fix 2023-02-24 21:56:29 +09:00
Stefan Holst b2953aef25 only dff 2023-02-22 13:37:15 +09:00
Stefan Holst 3774b14286 support ppi/ppo 2023-02-22 13:32:49 +09:00
Stefan Holst 4847ad9c40 locating io ports and busses by name 2023-02-21 23:26:48 +09:00
Stefan Holst 6801606dca new common scheduler for simulators 2023-02-21 19:27:54 +09:00
Stefan Holst faf41f0863 ff transitions switch 2023-02-06 09:53:44 +09:00
Stefan Holst 6430f10f73 HADD pin index fix 2023-02-06 09:52:32 +09:00
Stefan Holst fa19af8c31 4-input gate simulator 2023-01-18 14:34:17 +09:00
Stefan Holst 93a0858d2f oai and aoi pin handling fix 2023-01-16 17:37:41 +09:00
Stefan Holst 1f2808ee31 Merge branch 'main' into devel 2022-07-21 22:10:20 +09:00
Stefan Holst 163b348a0c year bump 2022-07-21 18:47:25 +09:00
Stefan Holst ecfc692edc support reset RN for scan cells 2022-07-21 17:16:59 +09:00
Stefan Holst afb7e745a1 adding aoi to logic sim 2022-07-21 17:16:59 +09:00
stefan 6a8841c3c6 revert wave_eval4 2022-07-21 16:57:20 +09:00
Stefan Holst c530983afa accept I as a first input 2022-03-17 14:57:37 +09:00
Stefan Holst 775b13c694 fix off-by-1 pin index when loading AOI and OAI cells 2022-02-02 15:05:14 +09:00
Stefan Holst 584445f3b1 wave eval for 4-input gates 2021-11-22 14:54:38 +09:00
Stefan Holst 85dd02d4d7 interpret N as unassigned in STIL 2021-11-07 18:51:41 +09:00
Stefan Holst 7c03271048 improve robustness of sdf annotation and wave sim 2021-09-01 12:57:55 +09:00
Stefan Holst 8bbaaf8fae comment change 2021-07-26 10:52:33 +09:00
Stefan Holst d59d6401c8 fix stil loading and logic sim capture 2021-07-22 17:21:58 +09:00
Stefan Holst 387c436207 fix tests, version bump 2021-07-19 14:14:35 +09:00
Stefan Holst b981b1153c add sdata to control individual sims 2021-06-17 12:05:55 +09:00
stefan 87d93afb44 fix time in unpickled log objects 2021-03-31 11:11:25 +09:00
Stefan Holst c3e4090f31 make nodes and lines hashable again 2021-03-28 19:44:19 +09:00
Stefan Holst 0251d66d28 make circuit pickable and comparable 2021-03-28 19:35:19 +09:00
Stefan Holst 864230b883 initial letch support, fix capture in logic sim 2021-03-25 10:36:55 +09:00
Stefan Holst d05841a6a2 Merge branch 'main' into devel 2021-01-31 18:32:14 +09:00
Stefan Holst c5be32d7e5 doc and indent fix 2021-01-31 18:25:09 +09:00
Stefan Holst 8434f5e694 fixes for IWLS benchmark netlists 2021-01-31 16:40:00 +09:00
Stefan Holst 9ff2369a55 fix parsing older stil files 2021-01-31 13:43:03 +09:00
Stefan Holst 82a53e0171 improve techlib for gsclib, better constant handling in verilog parser 2021-01-31 13:41:36 +09:00
Stefan Holst a2df0e5682 fix ff annotation 2021-01-22 18:03:18 +09:00
Stefan Holst ec37e11fef Merge branch 'main' into devel 2021-01-16 14:56:36 +09:00
Stefan Holst 3a5a3c128b year bump 2021-01-16 13:52:18 +09:00
Stefan Holst ee30898cef docs for numba and cuda 2021-01-16 13:35:20 +09:00
Stefan Holst 62cf56e98a TechLib class, remove unnecessary .index 2021-01-16 13:17:18 +09:00
Stefan Holst dc003fa624 documentation improvements 2021-01-16 00:04:34 +09:00
Stefan Holst 8b5a71f498 documentation improvements 2021-01-15 21:28:15 +09:00
Stefan Holst 9c8dee31b9 assign and capture return arrays, new cycle method for common use pattern 2021-01-14 20:47:22 +09:00
Stefan Holst 2bbdf3ee5d fix logic sim of DFF.QN output 2021-01-14 15:05:39 +09:00
Stefan Holst 35cf63cf38 Make Node and Line indexable, documentation. 2021-01-12 22:27:13 +09:00
Stefan Holst ff4de6d782 de-lint and repr improvements 2021-01-12 15:32:18 +09:00
Stefan Holst c12a30328c better hr_time 2021-01-12 15:18:37 +09:00
stefan 7e6660002b support ibuff in WaveSim 2021-01-06 15:58:47 +09:00
stefan dfbc35eeb9 logging range fixes 2021-01-06 13:56:03 +09:00
Stefan Holst 4f531fe4cb implement logging range 2021-01-06 12:54:14 +09:00
Stefan Holst 18c17b5f76 more docs and reprs 2021-01-06 11:32:43 +09:00
Stefan Holst 0bad95e94e LogicSim clean-up and new fault injection facility. version bump. 2020-12-22 19:01:19 +09:00
Stefan Holst 7501613951 remove comments 2020-12-21 20:23:53 +09:00
Stefan Holst 5084f1dd8c demo nb run with cuda 2020-12-21 20:13:48 +09:00
Stefan Holst 7f035c1ac5 Migration to new logic value representation 2020-12-21 19:16:52 +09:00
Stefan Holst 7bcfbf502b Documentation, cleanup, multi-valued logic 2020-12-20 17:44:04 +09:00
Stefan Holst 5830608527 Documenting circuit module 2020-12-18 21:14:00 +09:00
Stefan Holst cff18e0915 start documentation 2020-12-15 19:20:30 +09:00
Stefan Holst a77ac4a397 start designing new data structures for m-valued logic 2020-12-14 14:06:18 +09:00
5 changed files with 203 additions and 11 deletions

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@@ -20,11 +20,11 @@ sys.path.insert(0, os.path.abspath('../src'))
# -- Project information -----------------------------------------------------
project = 'KyuPy'
copyright = '2020-2025, Stefan Holst'
copyright = '2020-2026, Stefan Holst'
author = 'Stefan Holst'
# The full version, including alpha/beta/rc tags
release = '0.0.6'
release = '0.0.7'
# -- General configuration ---------------------------------------------------
+1 -1
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@@ -1,6 +1,6 @@
[project]
name = "kyupy"
version = "0.0.6"
version = "0.0.7"
authors = [
{ name="Stefan Holst", email="mail@s-holst.de" },
]
+1 -1
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@@ -448,7 +448,7 @@ class Circuit:
node_map[n] = Node(self, f'{node.name}~{n.name}', n.kind)
elif len(n.outs) > 0 and len(n.ins) > 0: # output is also read by impl. circuit, need to add a fork.
node_map[n] = Node(self, f'{node.name}~{n.name}')
elif len(n.ins) == 0 and len(n.outs) > 1: # input is read by multiple nodes, need to add fork.
elif len(n.ins) == 0 and len(n.outs) != 1: # input is read by multiple nodes (or no nodes), need to add fork.
node_map[n] = Node(self, f'{node.name}~{n.name}')
for l in impl.lines: # add all internal lines to main circuit
if l.reader in node_map and l.driver in node_map:
+191
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@@ -450,3 +450,194 @@ LATCHX{1,2}$ input(D,CLK) output(Q,QN) Q=LATCH(D,CLK) QN=INV1(Q) ;
"""The SAED 90nm educational technology library.
It defines all cells except: negative-edge flip-flops, tri-state, latches, clock gating, level shifters
"""
SKY130 = TechLib(r"""
$decap_{3,4,6,8,12} ;
$fill_{1,2,4,8} ;
$tap_{1,2} ;
$tapvgnd_1 ;
$tapvgnd2_1 ;
$tapvpwrvgnd_1 ;
$lpflow_decapkapwr_{3,4,6,8,12} ;
$lpflow_bleeder_1 input(SHORT) ;
$conb_1 output(HI,LO) HI=__const1__() LO=__const0__() ;
$macro_sparecell output(LO) LO=__const0__() ;
$diode_2 input(DIODE) ;
$probe_p_8 input(A) output(X) X=BUF1(A) ;
$probec_p_8 input(A) output(X) X=BUF1(A) ;
$inv_{1,2,4,6,8,12,16} input(A) output(Y) Y=INV1(A) ;
$buf_{1,2,4,6,8,12,16} input(A) output(X) X=BUF1(A) ;
$bufbuf_{8,16} input(A) output(X) X=BUF1(A) ;
$bufinv_{8,16} input(A) output(Y) Y=INV1(A) ;
$clkbuf_{1,2,4,8,16} input(A) output(X) X=BUF1(A) ;
$clkinv_{1,2,4,8,16} input(A) output(Y) Y=INV1(A) ;
$clkinvlp_{2,4} input(A) output(Y) Y=INV1(A) ;
$clkdlybuf4s15_{1,2} input(A) output(X) X=BUF1(A) ;
$clkdlybuf4s18_{1,2} input(A) output(X) X=BUF1(A) ;
$clkdlybuf4s25_{1,2} input(A) output(X) X=BUF1(A) ;
$clkdlybuf4s50_{1,2} input(A) output(X) X=BUF1(A) ;
$dlygate4sd1_1 input(A) output(X) X=BUF1(A) ;
$dlygate4sd2_1 input(A) output(X) X=BUF1(A) ;
$dlygate4sd3_1 input(A) output(X) X=BUF1(A) ;
$dlymetal6s2s_1 input(A) output(X) X=BUF1(A) ;
$dlymetal6s4s_1 input(A) output(X) X=BUF1(A) ;
$dlymetal6s6s_1 input(A) output(X) X=BUF1(A) ;
$lpflow_clkbufkapwr_{1,2,4,8,16} input(A) output(X) X=BUF1(A) ;
$lpflow_clkinvkapwr_{1,2,4,8,16} input(A) output(Y) Y=INV1(A) ;
$lpflow_lsbuf_lh_hl_isowell_tap_{1,2,4} input(A) output(X) X=BUF1(A) ;
$lpflow_lsbuf_lh_isowell_4 input(A) output(X) X=BUF1(A) ;
$lpflow_lsbuf_lh_isowell_tap_{1,2,4} input(A) output(X) X=BUF1(A) ;
$and2_{0,1,2,4} input(A,B) output(X) X=AND2(A,B) ;
$and2b_{1,2,4} input(A_N,B) output(X) AN=INV1(A_N) X=AND2(AN,B) ;
$and3_{1,2,4} input(A,B,C) output(X) X=AND3(A,B,C) ;
$and3b_{1,2,4} input(A_N,B,C) output(X) AN=INV1(A_N) X=AND3(AN,B,C) ;
$and4_{1,2,4} input(A,B,C,D) output(X) X=AND4(A,B,C,D) ;
$and4b_{1,2,4} input(A_N,B,C,D) output(X) AN=INV1(A_N) X=AND4(AN,B,C,D) ;
$and4bb_{1,2,4} input(A_N,B_N,C,D) output(X) AN=INV1(A_N) BN=INV1(B_N) X=AND4(AN,BN,C,D) ;
$or2_{0,1,2,4} input(A,B) output(X) X=OR2(A,B) ;
$or2b_{1,2,4} input(A,B_N) output(X) BN=INV1(B_N) X=OR2(A,BN) ;
$or3_{1,2,4} input(A,B,C) output(X) X=OR3(A,B,C) ;
$or3b_{1,2,4} input(A,B,C_N) output(X) CN=INV1(C_N) X=OR3(A,B,CN) ;
$or4_{1,2,4} input(A,B,C,D) output(X) X=OR4(A,B,C,D) ;
$or4b_{1,2,4} input(A,B,C,D_N) output(X) DN=INV1(D_N) X=OR4(A,B,C,DN) ;
$or4bb_{1,2,4} input(A,B,C_N,D_N) output(X) CN=INV1(C_N) DN=INV1(D_N) X=OR4(A,B,CN,DN) ;
$nand2_{1,2,4,8} input(A,B) output(Y) Y=NAND2(A,B) ;
$nand2b_{1,2,4} input(A_N,B) output(Y) AN=INV1(A_N) Y=NAND2(AN,B) ;
$nand3_{1,2,4} input(A,B,C) output(Y) Y=NAND3(A,B,C) ;
$nand3b_{1,2,4} input(A_N,B,C) output(Y) AN=INV1(A_N) Y=NAND3(AN,B,C) ;
$nand4_{1,2,4} input(A,B,C,D) output(Y) Y=NAND4(A,B,C,D) ;
$nand4b_{1,2,4} input(A_N,B,C,D) output(Y) AN=INV1(A_N) Y=NAND4(AN,B,C,D) ;
$nand4bb_{1,2,4} input(A_N,B_N,C,D) output(Y) AN=INV1(A_N) BN=INV1(B_N) Y=NAND4(AN,BN,C,D) ;
$nor2_{1,2,4,8} input(A,B) output(Y) Y=NOR2(A,B) ;
$nor2b_{1,2,4} input(A,B_N) output(Y) BN=INV1(B_N) Y=NOR2(A,BN) ;
$nor3_{1,2,4} input(A,B,C) output(Y) Y=NOR3(A,B,C) ;
$nor3b_{1,2,4} input(A,B,C_N) output(Y) CN=INV1(C_N) Y=NOR3(A,B,CN) ;
$nor4_{1,2,4} input(A,B,C,D) output(Y) Y=NOR4(A,B,C,D) ;
$nor4b_{1,2,4} input(A,B,C,D_N) output(Y) DN=INV1(D_N) Y=NOR4(A,B,C,DN) ;
$nor4bb_{1,2,4} input(A,B,C_N,D_N) output(Y) CN=INV1(C_N) DN=INV1(D_N) Y=NOR4(A,B,CN,DN) ;
$xor2_{1,2,4} input(A,B) output(X) X=XOR2(A,B) ;
$xor3_{1,2,4} input(A,B,C) output(X) X=XOR3(A,B,C) ;
$xnor2_{1,2,4} input(A,B) output(Y) Y=XNOR2(A,B) ;
$xnor3_{1,2,4} input(A,B,C) output(X) X=XNOR3(A,B,C) ;
$maj3_{1,2,4} input(A,B,C) output(X) AB=AND2(A,B) BC=AND2(B,C) AC=AND2(A,C) X=OR3(AB,BC,AC) ;
$mux2_{1,2,4,8} input(A0,A1,S) output(X) X=MUX21(A0,A1,S) ;
$mux2i_{1,2,4} input(A0,A1,S) output(Y) M=MUX21(A0,A1,S) Y=INV1(M) ;
$mux4_{1,2,4} input(A0,A1,A2,A3,S0,S1) output(X) M0=MUX21(A0,A1,S0) M1=MUX21(A2,A3,S0) X=MUX21(M0,M1,S1) ;
$ha_{1,2,4} input(A,B) output(COUT,SUM) SUM=XOR2(A,B) COUT=AND2(A,B) ;
$fa_{1,2,4} input(A,B,CIN) output(COUT,SUM) AB=XOR2(A,B) SUM=XOR2(AB,CIN) COUT=AO22(A,B,AB,CIN) ;
$fah_1 input(A,B,CI) output(COUT,SUM) AB=XOR2(A,B) SUM=XOR2(AB,CI) COUT=AO22(A,B,AB,CI) ;
$fahcin_1 input(A,B,CIN) output(COUT,SUM) AB=XOR2(A,B) SUM=XOR2(AB,CIN) COUT=AO22(A,B,AB,CIN) ;
$fahcon_1 input(A,B,CI) output(COUT_N,SUM) AB=XOR2(A,B) SUM=XOR2(AB,CI) T=AO22(A,B,AB,CI) COUT_N=INV1(T) ;
$a21o_{1,2,4} input(A1,A2,B1) output(X) X=AO21(A1,A2,B1) ;
$a21bo_{1,2,4} input(A1,A2,B1_N) output(X) BN=INV1(B1_N) X=AO21(A1,A2,BN) ;
$a22o_{1,2,4} input(A1,A2,B1,B2) output(X) X=AO22(A1,A2,B1,B2) ;
$a2bb2o_{1,2,4} input(A1_N,A2_N,B1,B2) output(X) AN1=INV1(A1_N) AN2=INV1(A2_N) X=AO22(AN1,AN2,B1,B2) ;
$a211o_{1,2,4} input(A1,A2,B1,C1) output(X) X=AO211(A1,A2,B1,C1) ;
$a221o_{1,2,4} input(A1,A2,B1,B2,C1) output(X) T=AO22(A1,A2,B1,B2) X=OR2(T,C1) ;
$a31o_{1,2,4} input(A1,A2,A3,B1) output(X) AA=AND3(A1,A2,A3) X=OR2(AA,B1) ;
$a311o_{1,2,4} input(A1,A2,A3,B1,C1) output(X) T=AND2(A1,A2) X=AO211(T,A3,B1,C1) ;
$a32o_{1,2,4} input(A1,A2,A3,B1,B2) output(X) T=AND2(A1,A2) X=AO22(T,A3,B1,B2) ;
$a41o_{1,2,4} input(A1,A2,A3,A4,B1) output(X) T1=AND2(A1,A2) T2=AND2(T1,A3) X=AO21(T2,A4,B1) ;
$a2111o_{1,2,4} input(A1,A2,B1,C1,D1) output(X) T=AO211(A1,A2,B1,C1) X=OR2(T,D1) ;
$a21oi_{1,2,4} input(A1,A2,B1) output(Y) Y=AOI21(A1,A2,B1) ;
$a21boi_{0,1,2,4} input(A1,A2,B1_N) output(Y) BN=INV1(B1_N) Y=AOI21(A1,A2,BN) ;
$a22oi_{1,2,4} input(A1,A2,B1,B2) output(Y) Y=AOI22(A1,A2,B1,B2) ;
$a2bb2oi_{1,2,4} input(A1_N,A2_N,B1,B2) output(Y) AN1=INV1(A1_N) AN2=INV1(A2_N) Y=AOI22(AN1,AN2,B1,B2) ;
$a211oi_{1,2,4} input(A1,A2,B1,C1) output(Y) Y=AOI211(A1,A2,B1,C1) ;
$a221oi_{1,2,4} input(A1,A2,B1,B2,C1) output(Y) T=AO22(A1,A2,B1,B2) Y=NOR2(T,C1) ;
$a222oi_1 input(A1,A2,B1,B2,C1,C2) output(Y) AB=AO22(A1,A2,B1,B2) Y=AOI21(C1,C2,AB) ;
$a31oi_{1,2,4} input(A1,A2,A3,B1) output(Y) AA=AND3(A1,A2,A3) Y=NOR2(AA,B1) ;
$a311oi_{1,2,4} input(A1,A2,A3,B1,C1) output(Y) T=AND2(A1,A2) Y=AOI211(T,A3,B1,C1) ;
$a32oi_{1,2,4} input(A1,A2,A3,B1,B2) output(Y) T=AND2(A1,A2) Y=AOI22(T,A3,B1,B2) ;
$a41oi_{1,2,4} input(A1,A2,A3,A4,B1) output(Y) T1=AND2(A1,A2) T2=AND2(T1,A3) Y=AOI21(T2,A4,B1) ;
$a2111oi_{0,1,2,4} input(A1,A2,B1,C1,D1) output(Y) T=AO211(A1,A2,B1,C1) Y=NOR2(T,D1) ;
$o21a_{1,2,4} input(A1,A2,B1) output(X) X=OA21(A1,A2,B1) ;
$o21ba_{1,2,4} input(A1,A2,B1_N) output(X) BN=INV1(B1_N) X=OA21(A1,A2,BN) ;
$o22a_{1,2,4} input(A1,A2,B1,B2) output(X) X=OA22(A1,A2,B1,B2) ;
$o2bb2a_{1,2,4} input(A1_N,A2_N,B1,B2) output(X) T=NAND2(A1_N,A2_N) X=OA21(B1,B2,T) ;
$o211a_{1,2,4} input(A1,A2,B1,C1) output(X) X=OA211(A1,A2,B1,C1) ;
$o221a_{1,2,4} input(A1,A2,B1,B2,C1) output(X) T=OA22(A1,A2,B1,B2) X=AND2(T,C1) ;
$o31a_{1,2,4} input(A1,A2,A3,B1) output(X) T=OR3(A1,A2,A3) X=AND2(T,B1) ;
$o311a_{1,2,4} input(A1,A2,A3,B1,C1) output(X) T=OR2(A1,A2) X=OA211(T,A3,B1,C1) ;
$o32a_{1,2,4} input(A1,A2,A3,B1,B2) output(X) T=OR3(A1,A2,A3) X=OA21(B1,B2,T) ;
$o41a_{1,2,4} input(A1,A2,A3,A4,B1) output(X) T=OR4(A1,A2,A3,A4) X=AND2(T,B1) ;
$o2111a_{1,2,4} input(A1,A2,B1,C1,D1) output(X) T=OA211(A1,A2,B1,C1) X=AND2(T,D1) ;
$o21ai_{0,1,2,4} input(A1,A2,B1) output(Y) Y=OAI21(A1,A2,B1) ;
$o21bai_{1,2,4} input(A1,A2,B1_N) output(Y) BN=INV1(B1_N) Y=OAI21(A1,A2,BN) ;
$o22ai_{1,2,4} input(A1,A2,B1,B2) output(Y) Y=OAI22(A1,A2,B1,B2) ;
$o2bb2ai_{1,2,4} input(A1_N,A2_N,B1,B2) output(Y) T=NAND2(A1_N,A2_N) Y=OAI21(B1,B2,T) ;
$o211ai_{1,2,4} input(A1,A2,B1,C1) output(Y) Y=OAI211(A1,A2,B1,C1) ;
$o221ai_{1,2,4} input(A1,A2,B1,B2,C1) output(Y) T=OA22(A1,A2,B1,B2) Y=NAND2(T,C1) ;
$o31ai_{1,2,4} input(A1,A2,A3,B1) output(Y) T=OR3(A1,A2,A3) Y=NAND2(T,B1) ;
$o311ai_{0,1,2,4} input(A1,A2,A3,B1,C1) output(Y) T=OR2(A1,A2) Y=OAI211(T,A3,B1,C1) ;
$o32ai_{1,2,4} input(A1,A2,A3,B1,B2) output(Y) T=OR3(A1,A2,A3) Y=OAI21(B1,B2,T) ;
$o41ai_{1,2,4} input(A1,A2,A3,A4,B1) output(Y) T=OR4(A1,A2,A3,A4) Y=NAND2(T,B1) ;
$o2111ai_{1,2,4} input(A1,A2,B1,C1,D1) output(Y) T=OA211(A1,A2,B1,C1) Y=NAND2(T,D1) ;
$dfxtp_{1,2,4} input(CLK,D) output(Q) Q=DFF(D,CLK) ;
$dfxbp_{1,2} input(CLK,D) output(Q,Q_N) Q=DFF(D,CLK) Q_N=INV1(Q) ;
$dfrtp_{1,2,4} input(CLK,D,RESET_B) output(Q) DR=AND2(D,RESET_B) Q=DFF(DR,CLK) ;
$dfrbp_{1,2} input(CLK,D,RESET_B) output(Q,Q_N) DR=AND2(D,RESET_B) Q=DFF(DR,CLK) Q_N=INV1(Q) ;
$dfstp_{1,2,4} input(CLK,D,SET_B) output(Q) S=INV1(SET_B) DS=OR2(D,S) Q=DFF(DS,CLK) ;
$dfsbp_{1,2} input(CLK,D,SET_B) output(Q,Q_N) S=INV1(SET_B) DS=OR2(D,S) Q=DFF(DS,CLK) Q_N=INV1(Q) ;
$dfbbp_1 input(CLK,D,SET_B,RESET_B) output(Q,Q_N) DR=AND2(D,RESET_B) S=INV1(SET_B) DRS=OR2(DR,S) Q=DFF(DRS,CLK) Q_N=INV1(Q) ;
$dfrtn_1 input(CLK_N,D,RESET_B) output(Q) CLKN=INV1(CLK_N) DR=AND2(D,RESET_B) Q=DFF(DR,CLKN) ;
$dfbbn_{1,2} input(CLK_N,D,SET_B,RESET_B) output(Q,Q_N) CLKN=INV1(CLK_N) DR=AND2(D,RESET_B) S=INV1(SET_B) DRS=OR2(DR,S) Q=DFF(DRS,CLKN) Q_N=INV1(Q) ;
$sdfxtp_{1,2,4} input(CLK,D,SCD,SCE) output(Q) DI=MUX21(D,SCD,SCE) Q=DFF(DI,CLK) ;
$sdfxbp_{1,2} input(CLK,D,SCD,SCE) output(Q,Q_N) DI=MUX21(D,SCD,SCE) Q=DFF(DI,CLK) Q_N=INV1(Q) ;
$sdfrtp_{1,2,4} input(CLK,D,SCD,SCE,RESET_B) output(Q) DR=AND2(D,RESET_B) DI=MUX21(DR,SCD,SCE) Q=DFF(DI,CLK) ;
$sdfrbp_{1,2} input(CLK,D,SCD,SCE,RESET_B) output(Q,Q_N) DR=AND2(D,RESET_B) DI=MUX21(DR,SCD,SCE) Q=DFF(DI,CLK) Q_N=INV1(Q) ;
$sdfstp_{1,2,4} input(CLK,D,SCD,SCE,SET_B) output(Q) S=INV1(SET_B) DS=OR2(D,S) DI=MUX21(DS,SCD,SCE) Q=DFF(DI,CLK) ;
$sdfsbp_{1,2} input(CLK,D,SCD,SCE,SET_B) output(Q,Q_N) S=INV1(SET_B) DS=OR2(D,S) DI=MUX21(DS,SCD,SCE) Q=DFF(DI,CLK) Q_N=INV1(Q) ;
$sdfbbp_1 input(CLK,D,SCD,SCE,SET_B,RESET_B) output(Q,Q_N) DR=AND2(D,RESET_B) S=INV1(SET_B) DRS=OR2(DR,S) DI=MUX21(DRS,SCD,SCE) Q=DFF(DI,CLK) Q_N=INV1(Q) ;
$sdfrtn_1 input(CLK_N,D,SCD,SCE,RESET_B) output(Q) CLKN=INV1(CLK_N) DR=AND2(D,RESET_B) DI=MUX21(DR,SCD,SCE) Q=DFF(DI,CLKN) ;
$sdfbbn_{1,2} input(CLK_N,D,SCD,SCE,SET_B,RESET_B) output(Q,Q_N) CLKN=INV1(CLK_N) DR=AND2(D,RESET_B) S=INV1(SET_B) DRS=OR2(DR,S) DI=MUX21(DRS,SCD,SCE) Q=DFF(DI,CLKN) Q_N=INV1(Q) ;
$edfxtp_1 input(CLK,D,DE) output(Q) GCK=AND2(CLK,DE) Q=DFF(D,GCK) ;
$edfxbp_1 input(CLK,D,DE) output(Q,Q_N) GCK=AND2(CLK,DE) Q=DFF(D,GCK) Q_N=INV1(Q) ;
$sedfxtp_{1,2,4} input(CLK,D,DE,SCD,SCE) output(Q) DI=MUX21(D,SCD,SCE) GCK=AND2(CLK,DE) Q=DFF(DI,GCK) ;
$sedfxbp_{1,2} input(CLK,D,DE,SCD,SCE) output(Q,Q_N) DI=MUX21(D,SCD,SCE) GCK=AND2(CLK,DE) Q=DFF(DI,GCK) Q_N=INV1(Q) ;
$dlxtp_1 input(D,GATE) output(Q) Q=LATCH(D,GATE) ;
$dlxtn_{1,2,4} input(D,GATE_N) output(Q) GN=INV1(GATE_N) Q=LATCH(D,GN) ;
$dlxbp_1 input(D,GATE) output(Q,Q_N) Q=LATCH(D,GATE) Q_N=INV1(Q) ;
$dlxbn_{1,2} input(D,GATE_N) output(Q,Q_N) GN=INV1(GATE_N) Q=LATCH(D,GN) Q_N=INV1(Q) ;
$dlrtp_{1,2,4} input(D,GATE,RESET_B) output(Q) DR=AND2(D,RESET_B) Q=LATCH(DR,GATE) ;
$dlrtn_{1,2,4} input(D,GATE_N,RESET_B) output(Q) GN=INV1(GATE_N) DR=AND2(D,RESET_B) Q=LATCH(DR,GN) ;
$dlrbp_{1,2} input(D,GATE,RESET_B) output(Q,Q_N) DR=AND2(D,RESET_B) Q=LATCH(DR,GATE) Q_N=INV1(Q) ;
$dlrbn_{1,2} input(D,GATE_N,RESET_B) output(Q,Q_N) GN=INV1(GATE_N) DR=AND2(D,RESET_B) Q=LATCH(DR,GN) Q_N=INV1(Q) ;
$dlclkp_{1,2,4} input(CLK,GATE) output(GCLK) GCLK=AND2(CLK,GATE) ;
$sdlclkp_{1,2,4} input(CLK,GATE,SCE) output(GCLK) G=OR2(GATE,SCE) GCLK=AND2(CLK,G) ;
$ebufn_{1,2,4,8} input(A,TE_B) output(Z) TE=INV1(TE_B) Z=AND2(A,TE) ;
$einvn_{0,1,2,4,8} input(A,TE_B) output(Z) TE=INV1(TE_B) ZI=INV1(A) Z=AND2(ZI,TE) ;
$einvp_{1,2,4,8} input(A,TE) output(Z) ZI=INV1(A) Z=AND2(ZI,TE) ;
$lpflow_inputiso0n_1 input(A,SLEEP_B) output(X) X=AND2(A,SLEEP_B) ;
$lpflow_inputiso0p_1 input(A,SLEEP) output(X) SB=INV1(SLEEP) X=AND2(A,SB) ;
$lpflow_inputiso1n_1 input(A,SLEEP_B) output(X) X=AND2(A,SLEEP_B) ;
$lpflow_inputiso1p_1 input(A,SLEEP) output(X) SB=INV1(SLEEP) X=AND2(A,SB) ;
$lpflow_isobufsrc_{1,2,4,8,16} input(A,SLEEP) output(X) AI=INV1(A) X=OR2(AI,SLEEP) ;
$lpflow_isobufsrckapwr_16 input(A,SLEEP) output(X) AI=INV1(A) X=OR2(AI,SLEEP) ;
$lpflow_inputisolatch_1 input(D,SLEEP_B) output(Q) Q=LATCH(D,SLEEP_B) ;
""".replace('$','sky130_fd_sc_hd__'))
"""SkyWater 130nm High Density Digital Standard Cells (skywater-pdk-libs-sky130_fd_sc_hd).
"""
+8 -7
View File
@@ -52,13 +52,14 @@ class VerilogTransformer(Transformer):
@staticmethod
def instantiation(args):
pinmap = {}
for idx, pin in enumerate(args[2:]):
p = pin.children[0]
if isinstance(p, tuple): # named pin
if p[1] is not None:
pinmap[p[0]] = p[1]
else: # unnamed pin
pinmap[idx] = p
if args[2] is not None:
for idx, pin in enumerate(args[2:]):
p = pin.children[0]
if isinstance(p, tuple): # named pin
if p[1] is not None:
pinmap[p[0]] = p[1]
else: # unnamed pin
pinmap[idx] = p
return Instantiation(args[0], args[1], pinmap)
@staticmethod