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doc and indent fix

devel
Stefan Holst 4 years ago
parent
commit
c5be32d7e5
  1. 4
      src/kyupy/logic_sim.py
  2. 2
      src/kyupy/verilog.py

4
src/kyupy/logic_sim.py

@ -107,10 +107,10 @@ class LogicSim: @@ -107,10 +107,10 @@ class LogicSim:
sim.capture(state_bp)
:param inject_cb: A callback function for manipulating intermediate signal values.
This function is called with a line index and its new logic values (in bit-parallel format) after
This function is called with a line and its new logic values (in bit-parallel format) after
evaluation of a node. The callback may manipulate the given values in-place, the simulation
resumes with the manipulated values after the callback returns.
:type inject_cb: ``f(int, ndarray)``
:type inject_cb: ``f(Line, ndarray)``
"""
for node in self.circuit.topological_order():
if self.state_epoch[node] != self.epoch: continue

2
src/kyupy/verilog.py

@ -52,7 +52,7 @@ class VerilogTransformer(Transformer): @@ -52,7 +52,7 @@ class VerilogTransformer(Transformer):
def instantiation(args):
return Instantiation(args[0], args[1],
dict((pin.children[0],
pin.children[1]) for pin in args[2:] if len(pin.children) > 1))
pin.children[1]) for pin in args[2:] if len(pin.children) > 1))
def range(self, args):
left = int(args[0].value)

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