From c5be32d7e5cfa9e66efd994916db0696aeeb5180 Mon Sep 17 00:00:00 2001 From: Stefan Holst Date: Sun, 31 Jan 2021 18:25:09 +0900 Subject: [PATCH] doc and indent fix --- src/kyupy/logic_sim.py | 4 ++-- src/kyupy/verilog.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/kyupy/logic_sim.py b/src/kyupy/logic_sim.py index 993938a..92641f2 100644 --- a/src/kyupy/logic_sim.py +++ b/src/kyupy/logic_sim.py @@ -107,10 +107,10 @@ class LogicSim: sim.capture(state_bp) :param inject_cb: A callback function for manipulating intermediate signal values. - This function is called with a line index and its new logic values (in bit-parallel format) after + This function is called with a line and its new logic values (in bit-parallel format) after evaluation of a node. The callback may manipulate the given values in-place, the simulation resumes with the manipulated values after the callback returns. - :type inject_cb: ``f(int, ndarray)`` + :type inject_cb: ``f(Line, ndarray)`` """ for node in self.circuit.topological_order(): if self.state_epoch[node] != self.epoch: continue diff --git a/src/kyupy/verilog.py b/src/kyupy/verilog.py index 45ca7c6..e8a20bd 100644 --- a/src/kyupy/verilog.py +++ b/src/kyupy/verilog.py @@ -52,7 +52,7 @@ class VerilogTransformer(Transformer): def instantiation(args): return Instantiation(args[0], args[1], dict((pin.children[0], - pin.children[1]) for pin in args[2:] if len(pin.children) > 1)) + pin.children[1]) for pin in args[2:] if len(pin.children) > 1)) def range(self, args): left = int(args[0].value)