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@ -126,6 +126,10 @@ class VerilogTransformer(Transformer):
@@ -126,6 +126,10 @@ class VerilogTransformer(Transformer):
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n = Node(c, stmt.name, kind=stmt.type) |
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for p, s in stmt.pins.items(): |
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if self.tlib.pin_is_output(n.kind, p): |
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if s in sig_decls: |
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s = sig_decls[s].names |
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if isinstance(s, list) and len(s) == 1: |
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s = s[0] |
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Line(c, (n, self.tlib.pin_index(stmt.type, p)), Node(c, s)) |
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elif hasattr(stmt, 'data') and stmt.data == 'assign': |
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assignments.append((stmt.children[0], stmt.children[1])) |
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@ -175,8 +179,11 @@ class VerilogTransformer(Transformer):
@@ -175,8 +179,11 @@ class VerilogTransformer(Transformer):
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s = cname |
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Line(c, cnode, Node(c, s)) |
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if s not in c.forks: |
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log.warn(f'Signal not driven: {s}') |
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Node(c, s) # generate fork here |
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if f'{s}[0]' in c.forks: # actually a 1-bit bus? |
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s = f'{s}[0]' |
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else: |
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log.warn(f'Signal not driven: {s}') |
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Node(c, s) # generate fork here |
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fork = c.forks[s] |
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if self.branchforks: |
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branchfork = Node(c, fork.name + "~" + n.name + "/" + p) |
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@ -187,9 +194,12 @@ class VerilogTransformer(Transformer):
@@ -187,9 +194,12 @@ class VerilogTransformer(Transformer):
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if sd.kind == 'output': |
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for name in sd.names: |
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if name not in c.forks: |
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log.warn(f'Output not driven: {name}') |
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else: |
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Line(c, c.forks[name], c.cells[name]) |
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if f'{name}[0]' in c.forks: # actually a 1-bit bus? |
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name = f'{name}[0]' |
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else: |
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log.warn(f'Output not driven: {name}') |
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continue |
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Line(c, c.forks[name], c.cells[name]) |
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return c |
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@staticmethod |
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