From 08d9f5a9bf35223556ff8593c6199073d5e8b770 Mon Sep 17 00:00:00 2001 From: Stefan Holst Date: Wed, 12 Jul 2023 16:32:08 +0900 Subject: [PATCH] one-bit busses --- src/kyupy/verilog.py | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/src/kyupy/verilog.py b/src/kyupy/verilog.py index 2d28034..0852786 100644 --- a/src/kyupy/verilog.py +++ b/src/kyupy/verilog.py @@ -126,6 +126,10 @@ class VerilogTransformer(Transformer): n = Node(c, stmt.name, kind=stmt.type) for p, s in stmt.pins.items(): if self.tlib.pin_is_output(n.kind, p): + if s in sig_decls: + s = sig_decls[s].names + if isinstance(s, list) and len(s) == 1: + s = s[0] Line(c, (n, self.tlib.pin_index(stmt.type, p)), Node(c, s)) elif hasattr(stmt, 'data') and stmt.data == 'assign': assignments.append((stmt.children[0], stmt.children[1])) @@ -175,8 +179,11 @@ class VerilogTransformer(Transformer): s = cname Line(c, cnode, Node(c, s)) if s not in c.forks: - log.warn(f'Signal not driven: {s}') - Node(c, s) # generate fork here + if f'{s}[0]' in c.forks: # actually a 1-bit bus? + s = f'{s}[0]' + else: + log.warn(f'Signal not driven: {s}') + Node(c, s) # generate fork here fork = c.forks[s] if self.branchforks: branchfork = Node(c, fork.name + "~" + n.name + "/" + p) @@ -187,9 +194,12 @@ class VerilogTransformer(Transformer): if sd.kind == 'output': for name in sd.names: if name not in c.forks: - log.warn(f'Output not driven: {name}') - else: - Line(c, c.forks[name], c.cells[name]) + if f'{name}[0]' in c.forks: # actually a 1-bit bus? + name = f'{name}[0]' + else: + log.warn(f'Output not driven: {name}') + continue + Line(c, c.forks[name], c.cells[name]) return c @staticmethod