stefan
f0b55eed27
version bump
2025-11-27 22:01:32 +09:00
stefan
3700ae9b33
need 3.12 for generic types
2025-11-27 21:59:06 +09:00
stefan
df695e0aa1
for release 0.0.6
...
- sim: added LogicSim2V, LogicSim4V, LogicSim6V (faster and simpler API)
- sim: fixed model for: many-input gates in bench; dangling nodes; POs that drive further logic
- Circuit: dot output fix and better style, fixed equivalence check of lines and nodes.
- Techlib: Added KYUPY library with supported simulation primitives for debug and testing
- tests: fixed and added more for better coverage
- more type annotations
- updated project config and dependencies for better uv experience, newer lark, newer numpy
2025-11-27 21:59:06 +09:00
stefan
a28128830d
beginning simple always block parsing in verilog
2025-11-27 21:19:59 +09:00
stefan
20cf441abb
add doc gen dependencies
2025-11-23 22:48:16 +09:00
stefan
5ac21edbb1
migrate readme to markdown
2025-11-23 22:39:31 +09:00
stefan
f0d74777af
add dff to techlib
2025-11-23 21:35:49 +09:00
stefan
3848665533
ignore more generated python files
2025-11-23 21:35:30 +09:00
stefan
541cccd756
fix sim model for PO that also drive further logic
2025-11-23 21:34:58 +09:00
stefan
fed66f85cb
fix oob in test
2025-11-23 21:31:56 +09:00
stefan
2eb10f83b0
add pytest dev dependency
2025-11-23 21:31:40 +09:00
stefan
dd4e5c861a
fix sim model generation for circuits with dangling nodes
2025-11-20 15:28:41 +09:00
stefan
9cebbcce8f
support for storing responses separately
2025-11-11 18:13:08 +09:00
stefan
31434cfd51
4v sim, fixed 6v sim, better testing
2025-11-09 08:09:46 +09:00
stefan
ce94210b52
adding more types
2025-11-09 08:08:03 +09:00
stefan
09420fd72c
new logic sim interface prototype, simprim lib and test
2025-11-02 20:56:14 +09:00
stefan
5bcc1c1d77
new synthetic techlib with kyupy simprims
2025-11-02 20:49:37 +09:00
stefan
df8a58f57b
generate proper simprims in bench parser
2025-11-02 20:44:04 +09:00
stefan
3dfd0cb60d
euivalence test, op format doc
2025-10-31 17:13:58 +09:00
stefan
21439e3595
circuit objects and nodes/lines of different circuits are not quivalent.
2025-10-31 17:12:50 +09:00
stefan
88a5c79161
dot fix and updated intro nb
2025-10-23 22:48:18 +09:00
stefan
9ca437fe47
fault injection for 4v sim, wave_sim test fix
2025-10-23 21:26:52 +09:00
stefan
0cdaf71963
fix for latest lark
2025-10-23 21:25:50 +09:00
stefan
75972d7bb2
numba config deprecated
2025-10-23 21:25:36 +09:00
stefan
469dc18aa9
lark dependency update
2025-10-23 18:20:29 +09:00
stefan
33addab141
fix output with newest numpy
2025-10-22 14:17:44 +09:00
stefan
674f3dea4a
Merge branch 'main' into devel
2025-06-23 16:06:02 +09:00
stefan
187d176cfd
partial ternary if support
2025-06-02 12:20:42 +09:00
stefan
ba1de0bea9
support for per-simulation delay factors
2025-01-17 13:17:44 +09:00
stefan
5769aa3716
deactivate delta sim
2025-01-17 11:28:12 +09:00
stefan
e97c370d39
support stuck-at fault model injection for 2-valued logic sim
2024-12-06 13:42:22 +09:00
stefan
3b7106be80
fix deferred assignments
2024-11-07 17:06:00 +09:00
stefan
d2357859f6
more robust matching and assign processing
2024-04-15 17:01:11 +09:00
stefan
53629c5c28
support injection into specific sims
2024-04-12 15:23:54 +09:00
stefan
e64845e8c0
fanout generator
2024-04-10 19:28:32 +09:00
stefan
da98ca2db7
signal flips in compiled code
2024-04-10 19:27:06 +09:00
stefan
deb4599206
fix tests
2024-04-08 23:21:24 +09:00
stefan
c1c9ec9aae
pin_name, cleanup legacy code
2024-04-08 16:35:21 +09:00
stefan
4c55dcec60
delta sim for improving fault sim performance
2024-04-08 00:29:12 +09:00
stefan
a4b7364478
mux21 in 6v logic sim, more test fixtures
2024-04-06 15:22:46 +09:00
stefan
f59e97afa9
remove hashes, add lst, overflow, ebuf
2024-04-05 23:24:00 +09:00
stefan
f6baf9cb5e
a fast 6v sim
2024-04-05 23:21:59 +09:00
stefan
fc030c6708
allow interconnect annotations without forks
2024-04-05 23:21:23 +09:00
Stefan Holst
795cac0716
initial and final values from mvarrays
2024-04-04 20:44:22 +09:00
Stefan Holst
3a8777e0a3
none-filtering iterator for GrowingList
2024-04-04 20:41:59 +09:00
Stefan Holst
68e8cb844a
pass line id to inject_cb
2024-02-16 09:48:52 +09:00
stefan
1a3b91c1c0
fix comment
2023-12-06 16:45:34 +09:00
Stefan Holst
aa7536b8b0
line use and diff
2023-12-06 16:44:17 +09:00
Stefan Holst
fccf5e0d84
fix log limit
2023-12-06 16:43:42 +09:00
Stefan Holst
a6d1e4099c
alap toposort, improve tests
2023-11-07 12:44:19 +09:00
Stefan Holst
1654915ed6
support for partial re-sim
2023-11-03 14:26:48 +09:00
Stefan Holst
d2a2484efa
fix fault injection
2023-11-03 14:26:04 +09:00
Stefan Holst
de79393dfc
fix log limiter, use eng notation
2023-09-26 13:58:38 +09:00
Stefan Holst
4bb3f3424a
cond in sdf parser. ignored for now.
2023-09-11 23:44:28 +09:00
Stefan Holst
a6243b43f6
keep s_nodes
2023-09-11 23:41:51 +09:00
Stefan Holst
baeb759824
types, perf op growing list, keep s_nodes
2023-08-07 21:59:08 +09:00
Stefan Holst
967a232b1c
fix pulse threshold selection
2023-07-29 09:45:48 +09:00
Stefan Holst
8096416b0e
save test position for each pattern
2023-07-28 17:26:28 +09:00
Stefan Holst
a4cce9f8c0
Produce stable value when trans. to/from -
2023-07-28 17:20:34 +09:00
Stefan Holst
4f6b733eb4
fix NanGate variants, version bump
2023-07-26 17:18:28 +09:00
Stefan Holst
371bc906b3
Merge branch 'main' into devel
...
fix readthedocs
2023-07-22 17:09:46 +09:00
Stefan Holst
0ade89defa
remove old test data, intro check
2023-07-22 15:58:16 +09:00
Stefan Holst
7f4026f504
def-file docs
2023-07-22 15:52:51 +09:00
Stefan Holst
e6a0d59d44
def-file docs
2023-07-22 15:52:28 +09:00
Stefan Holst
63e5f32e21
better ignore
2023-07-22 13:24:25 +09:00
Stefan Holst
35e727e714
better docs, new techlib as default, fix tests
2023-07-22 13:11:11 +09:00
Stefan Holst
83445e2bbd
support for newer NANGATE lib
2023-07-21 22:14:29 +09:00
Stefan Holst
c67148c0ee
doc fix
2023-07-21 22:13:25 +09:00
Stefan Holst
280c425486
fix test
2023-07-12 22:35:53 +09:00
Stefan Holst
5be82da49a
avoid holes in forks, update intro
2023-07-12 22:32:22 +09:00
Stefan Holst
b3dbe9765a
fix xor in libs, remove old code
2023-07-12 21:10:27 +09:00
Stefan Holst
5e573b0408
fix substitute for inputs with fo, dot graph
2023-07-12 21:06:16 +09:00
Stefan Holst
08d9f5a9bf
one-bit busses
2023-07-12 16:32:08 +09:00
Stefan Holst
b098fb219d
fix for unconnected named pins, double-declaration
2023-07-12 11:36:43 +09:00
Stefan Holst
97387e962b
add GSC180nm
2023-07-12 11:35:15 +09:00
Stefan Holst
f4d875f7e5
docs
2023-07-12 11:34:45 +09:00
Stefan Holst
cf9a98b5ce
del deprecated sdf code, explicit tlib use
2023-07-10 20:35:19 +09:00
Stefan Holst
d8f605a47a
fix double-free when fo goes to same cell
2023-07-10 20:08:48 +09:00
Stefan Holst
ec5626b8ca
remove old connections in substitute node reuse
2023-07-10 09:00:31 +09:00
Stefan Holst
5a693f7b9b
preserve node order during resolve
2023-07-09 23:46:14 +09:00
Stefan Holst
19bbe2c260
update intro
2023-07-09 21:34:01 +09:00
Stefan Holst
d3897246c5
move resolving cells to circuit, more doc
2023-07-09 19:04:22 +09:00
Stefan Holst
9bda7a4c57
capitalize tech libs
2023-07-09 19:01:31 +09:00
Stefan Holst
2270a9eee7
fix fork stripping + fork None values
2023-07-09 19:01:15 +09:00
Stefan Holst
ea45a326ec
add latch, fix xor delays, improve test
2023-07-09 13:42:07 +09:00
Stefan Holst
1e9fe7707b
saed32nm
2023-07-09 00:29:56 +09:00
Stefan Holst
50a5d8a290
one cell inherits name in substitute, sim fix
2023-07-08 22:52:10 +09:00
Stefan Holst
d97555e9e9
fix simprim cells, add saed90
2023-07-08 18:55:52 +09:00
Stefan Holst
47ee8d5878
improve substitute, update notebook output
2023-07-08 18:54:27 +09:00
Stefan Holst
c32584fc76
1to1 fork optimization, fix substitute
2023-07-05 22:55:06 +09:00
Stefan Holst
39b8c1695b
full constants support, fix signal declarations
2023-07-05 22:07:15 +09:00
Stefan Holst
80d26b6f0b
Add AO*211 and OA*211, fix MUX21
2023-07-05 22:01:42 +09:00
Stefan Holst
f7ef78e58d
support for limiting log messages
2023-07-05 21:59:49 +09:00
Stefan Holst
7afb13b33b
mv_str for single values, remove undue assert
2023-07-03 12:40:02 +09:00
Stefan Holst
153442a10a
def file parser
2023-07-03 00:49:23 +09:00
Stefan Holst
afb0a64953
wsa accumulation in wavesim
2023-07-03 00:48:58 +09:00
Stefan Holst
c49667edc1
remove old code, verilog positional pins
2023-06-26 23:23:56 +09:00
Stefan Holst
d921eb5048
sim support for remaining primitives
2023-06-25 22:27:19 +09:00
Stefan Holst
670fb0b3fc
circuit node substitution
2023-06-25 22:26:52 +09:00
Stefan Holst
f8bf579be2
support concat, bus select, ISOL cells
2023-06-24 23:41:08 +09:00
Stefan Holst
f61e2b42e8
support more cells in logic sim
2023-06-24 13:34:35 +09:00
Stefan Holst
4aec335abb
verilog: concat assignments, more comments
2023-06-24 13:33:55 +09:00
Stefan Holst
1a9cb396bf
tweak repr, doc
2023-06-24 13:32:40 +09:00
Stefan Holst
3875dc38f9
docs
2023-06-21 23:23:01 +09:00
Stefan Holst
ecb7171c37
docs
2023-06-21 23:18:17 +09:00
Stefan Holst
8957db48ab
docs
2023-06-20 06:54:59 +09:00
Stefan Holst
0b15f9fa18
doc improvements
2023-06-19 17:05:39 +09:00
Stefan Holst
dc76a9f517
new into demo
2023-06-19 14:01:31 +09:00
Stefan Holst
0968cb451e
docs, fix stil unassigned, fix io_locs for busses
2023-06-19 13:12:17 +09:00
Stefan Holst
947df89434
add AOI21 to logic sim
2023-06-02 00:04:34 +09:00
Stefan Holst
f17e461fdd
fix reading directly from file handle
2023-05-19 14:57:02 +09:00
Stefan Holst
d6d981a351
support for det vars
2023-04-05 18:35:55 +09:00
Stefan Holst
7a060b1831
support for static variations
2023-03-28 11:10:38 +09:00
Stefan Holst
03802ac9f8
make sims pickleable
2023-03-22 13:55:53 +09:00
Stefan Holst
70caea065e
more cleanup
2023-03-20 14:14:06 +09:00
stefan
f04f1b0012
cleanup
2023-03-20 10:31:55 +09:00
Stefan Holst
44b0c887d7
random sampling of delays
2023-03-19 20:30:27 +09:00
Stefan Holst
4e2022291e
fix cuda ppo_to_ppi
2023-03-15 15:15:22 +09:00
Stefan Holst
5566b80e52
simprim, vat refactor, batchrange
2023-03-15 10:37:39 +09:00
stefan
63c0b48537
bump
2023-03-14 18:50:15 +09:00
stefan
6520ee23ef
cleanup and new intro notebook
2023-03-14 17:40:50 +09:00
stefan
1810d40959
pytest work without cuda
2023-03-13 23:18:32 +09:00
Stefan Holst
7430ebb068
jitted logic sim
2023-03-13 23:15:20 +09:00
stefan
89f317b463
better circuit statsu, 2v logic sim
2023-03-13 10:50:44 +09:00
Stefan Holst
753ce566e4
Timer improvements, log in yaml
2023-03-13 10:45:41 +09:00
stefan
1eb8d87884
faster logic sim, removing MVArray, BPArray
2023-03-12 23:59:10 +09:00
stefan
02f3a0e1b2
correct timing padding
2023-02-28 09:39:01 +09:00
stefan
fc8e65e788
bit-packing utility
2023-02-28 09:38:28 +09:00
stefan
d80a3ae2b1
timer utility
2023-02-28 09:38:02 +09:00
Stefan Holst
7bfc02e683
more on-gpu code, bump python requirement
2023-02-26 22:37:15 +09:00
Stefan Holst
8da4a62bce
switch to new wave_sim, silence occupancy warnings
2023-02-26 13:54:01 +09:00
stefan
3497bfdc75
first gpu-code, cached test fixtures
2023-02-26 13:09:49 +09:00
stefan
f1ebe1487c
new wave sim
2023-02-26 11:04:38 +09:00
stefan
f0dac36ac7
interface -> io_nodes, io_loc fix
2023-02-24 21:56:29 +09:00
Stefan Holst
b2953aef25
only dff
2023-02-22 13:37:15 +09:00
Stefan Holst
3774b14286
support ppi/ppo
2023-02-22 13:32:49 +09:00
Stefan Holst
4847ad9c40
locating io ports and busses by name
2023-02-21 23:26:48 +09:00
Stefan Holst
6801606dca
new common scheduler for simulators
2023-02-21 19:27:54 +09:00
Stefan Holst
faf41f0863
ff transitions switch
2023-02-06 09:53:44 +09:00
Stefan Holst
6430f10f73
HADD pin index fix
2023-02-06 09:52:32 +09:00
Stefan Holst
fa19af8c31
4-input gate simulator
2023-01-18 14:34:17 +09:00
Stefan Holst
93a0858d2f
oai and aoi pin handling fix
2023-01-16 17:37:41 +09:00
Stefan Holst
1f2808ee31
Merge branch 'main' into devel
2022-07-21 22:10:20 +09:00
Stefan Holst
163b348a0c
year bump
2022-07-21 18:47:25 +09:00
Stefan Holst
ecfc692edc
support reset RN for scan cells
2022-07-21 17:16:59 +09:00
Stefan Holst
afb7e745a1
adding aoi to logic sim
2022-07-21 17:16:59 +09:00
stefan
6a8841c3c6
revert wave_eval4
2022-07-21 16:57:20 +09:00
Stefan Holst
c530983afa
accept I as a first input
2022-03-17 14:57:37 +09:00
Stefan Holst
775b13c694
fix off-by-1 pin index when loading AOI and OAI cells
2022-02-02 15:05:14 +09:00
Stefan Holst
584445f3b1
wave eval for 4-input gates
2021-11-22 14:54:38 +09:00
Stefan Holst
85dd02d4d7
interpret N as unassigned in STIL
2021-11-07 18:51:41 +09:00
Stefan Holst
7c03271048
improve robustness of sdf annotation and wave sim
2021-09-01 12:57:55 +09:00
Stefan Holst
8bbaaf8fae
comment change
2021-07-26 10:52:33 +09:00
Stefan Holst
d59d6401c8
fix stil loading and logic sim capture
2021-07-22 17:21:58 +09:00
Stefan Holst
387c436207
fix tests, version bump
2021-07-19 14:14:35 +09:00
Stefan Holst
b981b1153c
add sdata to control individual sims
2021-06-17 12:05:55 +09:00
stefan
87d93afb44
fix time in unpickled log objects
2021-03-31 11:11:25 +09:00
Stefan Holst
c3e4090f31
make nodes and lines hashable again
2021-03-28 19:44:19 +09:00
Stefan Holst
0251d66d28
make circuit pickable and comparable
2021-03-28 19:35:19 +09:00
Stefan Holst
864230b883
initial letch support, fix capture in logic sim
2021-03-25 10:36:55 +09:00
Stefan Holst
d05841a6a2
Merge branch 'main' into devel
2021-01-31 18:32:14 +09:00
Stefan Holst
c5be32d7e5
doc and indent fix
2021-01-31 18:25:09 +09:00
Stefan Holst
8434f5e694
fixes for IWLS benchmark netlists
2021-01-31 16:40:00 +09:00
Stefan Holst
9ff2369a55
fix parsing older stil files
2021-01-31 13:43:03 +09:00
Stefan Holst
82a53e0171
improve techlib for gsclib, better constant handling in verilog parser
2021-01-31 13:41:36 +09:00
Stefan Holst
a2df0e5682
fix ff annotation
2021-01-22 18:03:18 +09:00
Stefan Holst
ec37e11fef
Merge branch 'main' into devel
2021-01-16 14:56:36 +09:00
Stefan Holst
3a5a3c128b
year bump
2021-01-16 13:52:18 +09:00
Stefan Holst
ee30898cef
docs for numba and cuda
2021-01-16 13:35:20 +09:00
Stefan Holst
62cf56e98a
TechLib class, remove unnecessary .index
2021-01-16 13:17:18 +09:00
Stefan Holst
dc003fa624
documentation improvements
2021-01-16 00:04:34 +09:00
Stefan Holst
8b5a71f498
documentation improvements
2021-01-15 21:28:15 +09:00
Stefan Holst
9c8dee31b9
assign and capture return arrays, new cycle method for common use pattern
2021-01-14 20:47:22 +09:00
Stefan Holst
2bbdf3ee5d
fix logic sim of DFF.QN output
2021-01-14 15:05:39 +09:00
Stefan Holst
35cf63cf38
Make Node and Line indexable, documentation.
2021-01-12 22:27:13 +09:00
Stefan Holst
ff4de6d782
de-lint and repr improvements
2021-01-12 15:32:18 +09:00
Stefan Holst
c12a30328c
better hr_time
2021-01-12 15:18:37 +09:00
stefan
7e6660002b
support ibuff in WaveSim
2021-01-06 15:58:47 +09:00
stefan
dfbc35eeb9
logging range fixes
2021-01-06 13:56:03 +09:00
Stefan Holst
4f531fe4cb
implement logging range
2021-01-06 12:54:14 +09:00
Stefan Holst
18c17b5f76
more docs and reprs
2021-01-06 11:32:43 +09:00
Stefan Holst
0bad95e94e
LogicSim clean-up and new fault injection facility. version bump.
2020-12-22 19:01:19 +09:00
Stefan Holst
7501613951
remove comments
2020-12-21 20:23:53 +09:00
Stefan Holst
5084f1dd8c
demo nb run with cuda
2020-12-21 20:13:48 +09:00
Stefan Holst
7f035c1ac5
Migration to new logic value representation
2020-12-21 19:16:52 +09:00
Stefan Holst
7bcfbf502b
Documentation, cleanup, multi-valued logic
2020-12-20 17:44:04 +09:00
Stefan Holst
5830608527
Documenting circuit module
2020-12-18 21:14:00 +09:00
Stefan Holst
cff18e0915
start documentation
2020-12-15 19:20:30 +09:00
Stefan Holst
a77ac4a397
start designing new data structures for m-valued logic
2020-12-14 14:06:18 +09:00