967a232b1c
fix pulse threshold selection
1 year ago
8096416b0e
save test position for each pattern
1 year ago
a4cce9f8c0
Produce stable value when trans. to/from -
1 year ago
4f6b733eb4
fix NanGate variants, version bump
1 year ago
371bc906b3
Merge branch 'main' into devel
...
fix readthedocs
1 year ago
9f9902c613
remove _static
1 year ago
eb4e0f4529
improve readthedocs config
1 year ago
821ead0c7a
add readthedocs conf for py3.8
1 year ago
351d809306
for release 0.0.4
...
- Circuit: is now pickleable and comparable
- Circuit: utilities for locating/indexing io-ports
- Verilog: parser fixes, support yosys-style verilog
- SDF: parser fixes, full XOR support
- STIL: parser fixes
- Simulators: faster, up to 4-input cells, pickleable
- WaveSim: WSA calculation support
- WaveSim: Per-simulation parameters and delays
- Logic: Data are now raw numpy arrays
- Logic: More tools for bit-packing
- Added DEF parser
- Better techlib support for NanGate, SAED, GSC180
- Tests and docs improvements
1 year ago
0ade89defa
remove old test data, intro check
1 year ago
7f4026f504
def-file docs
1 year ago
e6a0d59d44
def-file docs
1 year ago
63e5f32e21
better ignore
1 year ago
35e727e714
better docs, new techlib as default, fix tests
1 year ago
83445e2bbd
support for newer NANGATE lib
1 year ago
c67148c0ee
doc fix
1 year ago
280c425486
fix test
1 year ago
5be82da49a
avoid holes in forks, update intro
1 year ago
b3dbe9765a
fix xor in libs, remove old code
1 year ago
5e573b0408
fix substitute for inputs with fo, dot graph
1 year ago
08d9f5a9bf
one-bit busses
1 year ago
b098fb219d
fix for unconnected named pins, double-declaration
1 year ago
97387e962b
add GSC180nm
1 year ago
f4d875f7e5
docs
1 year ago
cf9a98b5ce
del deprecated sdf code, explicit tlib use
1 year ago
d8f605a47a
fix double-free when fo goes to same cell
1 year ago
ec5626b8ca
remove old connections in substitute node reuse
1 year ago
5a693f7b9b
preserve node order during resolve
1 year ago
19bbe2c260
update intro
1 year ago
d3897246c5
move resolving cells to circuit, more doc
1 year ago
9bda7a4c57
capitalize tech libs
1 year ago
2270a9eee7
fix fork stripping + fork None values
1 year ago
ea45a326ec
add latch, fix xor delays, improve test
1 year ago
1e9fe7707b
saed32nm
1 year ago
50a5d8a290
one cell inherits name in substitute, sim fix
1 year ago
d97555e9e9
fix simprim cells, add saed90
1 year ago
47ee8d5878
improve substitute, update notebook output
1 year ago
c32584fc76
1to1 fork optimization, fix substitute
1 year ago
39b8c1695b
full constants support, fix signal declarations
1 year ago
80d26b6f0b
Add AO*211 and OA*211, fix MUX21
1 year ago
f7ef78e58d
support for limiting log messages
1 year ago
7afb13b33b
mv_str for single values, remove undue assert
1 year ago
153442a10a
def file parser
1 year ago
afb0a64953
wsa accumulation in wavesim
1 year ago
c49667edc1
remove old code, verilog positional pins
2 years ago
d921eb5048
sim support for remaining primitives
2 years ago
670fb0b3fc
circuit node substitution
2 years ago
f8bf579be2
support concat, bus select, ISOL cells
2 years ago
f61e2b42e8
support more cells in logic sim
2 years ago
4aec335abb
verilog: concat assignments, more comments
2 years ago
Stefan Holst