Stefan Holst
fc030c6708
allow interconnect annotations without forks
9 months ago
Stefan Holst
795cac0716
initial and final values from mvarrays
9 months ago
Stefan Holst
3a8777e0a3
none-filtering iterator for GrowingList
9 months ago
Stefan Holst
68e8cb844a
pass line id to inject_cb
10 months ago
Stefan Holst
1a3b91c1c0
fix comment
1 year ago
Stefan Holst
aa7536b8b0
line use and diff
1 year ago
Stefan Holst
fccf5e0d84
fix log limit
1 year ago
Stefan Holst
a6d1e4099c
alap toposort, improve tests
1 year ago
Stefan Holst
1654915ed6
support for partial re-sim
1 year ago
Stefan Holst
d2a2484efa
fix fault injection
1 year ago
Stefan Holst
de79393dfc
fix log limiter, use eng notation
1 year ago
Stefan Holst
4bb3f3424a
cond in sdf parser. ignored for now.
1 year ago
Stefan Holst
a6243b43f6
keep s_nodes
1 year ago
Stefan Holst
baeb759824
types, perf op growing list, keep s_nodes
1 year ago
Stefan Holst
967a232b1c
fix pulse threshold selection
1 year ago
Stefan Holst
8096416b0e
save test position for each pattern
1 year ago
Stefan Holst
a4cce9f8c0
Produce stable value when trans. to/from -
1 year ago
Stefan Holst
4f6b733eb4
fix NanGate variants, version bump
1 year ago
Stefan Holst
371bc906b3
Merge branch 'main' into devel
...
fix readthedocs
1 year ago
Stefan Holst
9f9902c613
remove _static
1 year ago
Stefan Holst
eb4e0f4529
improve readthedocs config
1 year ago
Stefan Holst
821ead0c7a
add readthedocs conf for py3.8
1 year ago
Stefan Holst
351d809306
for release 0.0.4
...
- Circuit: is now pickleable and comparable
- Circuit: utilities for locating/indexing io-ports
- Verilog: parser fixes, support yosys-style verilog
- SDF: parser fixes, full XOR support
- STIL: parser fixes
- Simulators: faster, up to 4-input cells, pickleable
- WaveSim: WSA calculation support
- WaveSim: Per-simulation parameters and delays
- Logic: Data are now raw numpy arrays
- Logic: More tools for bit-packing
- Added DEF parser
- Better techlib support for NanGate, SAED, GSC180
- Tests and docs improvements
1 year ago
Stefan Holst
0ade89defa
remove old test data, intro check
1 year ago
Stefan Holst
7f4026f504
def-file docs
1 year ago
Stefan Holst
e6a0d59d44
def-file docs
1 year ago
Stefan Holst
63e5f32e21
better ignore
1 year ago
Stefan Holst
35e727e714
better docs, new techlib as default, fix tests
1 year ago
Stefan Holst
83445e2bbd
support for newer NANGATE lib
1 year ago
Stefan Holst
c67148c0ee
doc fix
1 year ago
Stefan Holst
280c425486
fix test
1 year ago
Stefan Holst
5be82da49a
avoid holes in forks, update intro
1 year ago
Stefan Holst
b3dbe9765a
fix xor in libs, remove old code
1 year ago
Stefan Holst
5e573b0408
fix substitute for inputs with fo, dot graph
1 year ago
Stefan Holst
08d9f5a9bf
one-bit busses
1 year ago
Stefan Holst
b098fb219d
fix for unconnected named pins, double-declaration
1 year ago
Stefan Holst
97387e962b
add GSC180nm
1 year ago
Stefan Holst
f4d875f7e5
docs
1 year ago
Stefan Holst
cf9a98b5ce
del deprecated sdf code, explicit tlib use
1 year ago
Stefan Holst
d8f605a47a
fix double-free when fo goes to same cell
1 year ago
Stefan Holst
ec5626b8ca
remove old connections in substitute node reuse
1 year ago
Stefan Holst
5a693f7b9b
preserve node order during resolve
1 year ago
Stefan Holst
19bbe2c260
update intro
1 year ago
Stefan Holst
d3897246c5
move resolving cells to circuit, more doc
1 year ago
Stefan Holst
9bda7a4c57
capitalize tech libs
1 year ago
Stefan Holst
2270a9eee7
fix fork stripping + fork None values
1 year ago
Stefan Holst
ea45a326ec
add latch, fix xor delays, improve test
1 year ago
Stefan Holst
1e9fe7707b
saed32nm
1 year ago
Stefan Holst
50a5d8a290
one cell inherits name in substitute, sim fix
1 year ago
Stefan Holst
d97555e9e9
fix simprim cells, add saed90
1 year ago