Stefan Holst
faf41f0863
ff transitions switch
2023-02-06 09:53:44 +09:00
Stefan Holst
6430f10f73
HADD pin index fix
2023-02-06 09:52:32 +09:00
Stefan Holst
fa19af8c31
4-input gate simulator
2023-01-18 14:34:17 +09:00
Stefan Holst
93a0858d2f
oai and aoi pin handling fix
2023-01-16 17:37:41 +09:00
Stefan Holst
1f2808ee31
Merge branch 'main' into devel
2022-07-21 22:10:20 +09:00
Stefan Holst
840b816804
Circuit pickle, STIL/SDF/techlib fixes, sdata
...
- fix pin indices for various SC lib variants
- SDF annotation improvements
- STIL loading improvements
- Support for per-simulation parameters in WaveSim
- Circuit is now pickleable and comparable
2022-07-21 22:01:51 +09:00
Stefan Holst
163b348a0c
year bump
2022-07-21 18:47:25 +09:00
Stefan Holst
ecfc692edc
support reset RN for scan cells
2022-07-21 17:16:59 +09:00
Stefan Holst
afb7e745a1
adding aoi to logic sim
2022-07-21 17:16:59 +09:00
stefan
6a8841c3c6
revert wave_eval4
2022-07-21 16:57:20 +09:00
Stefan Holst
c530983afa
accept I as a first input
2022-03-17 14:57:37 +09:00
Stefan Holst
775b13c694
fix off-by-1 pin index when loading AOI and OAI cells
2022-02-02 15:05:14 +09:00
Stefan Holst
584445f3b1
wave eval for 4-input gates
2021-11-22 14:54:38 +09:00
Stefan Holst
85dd02d4d7
interpret N as unassigned in STIL
2021-11-07 18:51:41 +09:00
Stefan Holst
7c03271048
improve robustness of sdf annotation and wave sim
2021-09-01 12:57:55 +09:00
Stefan Holst
8bbaaf8fae
comment change
2021-07-26 10:52:33 +09:00
Stefan Holst
d59d6401c8
fix stil loading and logic sim capture
2021-07-22 17:21:58 +09:00
Stefan Holst
387c436207
fix tests, version bump
2021-07-19 14:14:35 +09:00
Stefan Holst
b981b1153c
add sdata to control individual sims
2021-06-17 12:05:55 +09:00
stefan
87d93afb44
fix time in unpickled log objects
2021-03-31 11:11:25 +09:00
Stefan Holst
c3e4090f31
make nodes and lines hashable again
2021-03-28 19:44:19 +09:00
Stefan Holst
0251d66d28
make circuit pickable and comparable
2021-03-28 19:35:19 +09:00
Stefan Holst
864230b883
initial letch support, fix capture in logic sim
2021-03-25 10:36:55 +09:00
Stefan Holst
d05841a6a2
Merge branch 'main' into devel
2021-01-31 18:32:14 +09:00
Stefan Holst
b17ab2d148
fixes for IWLS benchmark netlists and older STIL files
2021-01-31 18:28:56 +09:00
Stefan Holst
c5be32d7e5
doc and indent fix
2021-01-31 18:25:09 +09:00
Stefan Holst
8434f5e694
fixes for IWLS benchmark netlists
2021-01-31 16:40:00 +09:00
Stefan Holst
9ff2369a55
fix parsing older stil files
2021-01-31 13:43:03 +09:00
Stefan Holst
82a53e0171
improve techlib for gsclib, better constant handling in verilog parser
2021-01-31 13:41:36 +09:00
Stefan Holst
a2df0e5682
fix ff annotation
2021-01-22 18:03:18 +09:00
Stefan Holst
ec37e11fef
Merge branch 'main' into devel
2021-01-16 14:56:36 +09:00
Stefan Holst
c9445f2d79
Docs, __index__, fault injection and TechLib
...
- Documentation improvements
- Node and Line objects now provide __index__
- LogicSim cleanup and improvements (inject_cb, cycle, ...)
- Introduce TechLib class to organize tech-specific info
- More human-readable output
- De-linting
2021-01-16 14:48:27 +09:00
Stefan Holst
3a5a3c128b
year bump
2021-01-16 13:52:18 +09:00
Stefan Holst
ee30898cef
docs for numba and cuda
2021-01-16 13:35:20 +09:00
Stefan Holst
62cf56e98a
TechLib class, remove unnecessary .index
2021-01-16 13:17:18 +09:00
Stefan Holst
dc003fa624
documentation improvements
2021-01-16 00:04:34 +09:00
Stefan Holst
8b5a71f498
documentation improvements
2021-01-15 21:28:15 +09:00
Stefan Holst
9c8dee31b9
assign and capture return arrays, new cycle method for common use pattern
2021-01-14 20:47:22 +09:00
Stefan Holst
2bbdf3ee5d
fix logic sim of DFF.QN output
2021-01-14 15:05:39 +09:00
Stefan Holst
35cf63cf38
Make Node and Line indexable, documentation.
2021-01-12 22:27:13 +09:00
Stefan Holst
ff4de6d782
de-lint and repr improvements
2021-01-12 15:32:18 +09:00
Stefan Holst
c12a30328c
better hr_time
2021-01-12 15:18:37 +09:00
stefan
7e6660002b
support ibuff in WaveSim
2021-01-06 15:58:47 +09:00
stefan
dfbc35eeb9
logging range fixes
2021-01-06 13:56:03 +09:00
Stefan Holst
4f531fe4cb
implement logging range
2021-01-06 12:54:14 +09:00
Stefan Holst
18c17b5f76
more docs and reprs
2021-01-06 11:32:43 +09:00
Stefan Holst
0bad95e94e
LogicSim clean-up and new fault injection facility. version bump.
2020-12-22 19:01:19 +09:00
Stefan Holst
64e1de396f
New m-valued logic arrays, documentation, 0.0.2
...
- MVArray for multi-valued logic
- BPArray for bit-parallel storage layout
- Started documenting with Sphinx
- Migrated simulators to new BPArray
2020-12-21 20:44:23 +09:00
Stefan Holst
7501613951
remove comments
2020-12-21 20:23:53 +09:00
Stefan Holst
5084f1dd8c
demo nb run with cuda
2020-12-21 20:13:48 +09:00
Stefan Holst
stefan