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Author	SHA1	Message	Date
Stefan Holst	cf9a98b5ce	del deprecated sdf code, explicit tlib use	2023-07-10 20:35:19 +09:00
Stefan Holst	d8f605a47a	fix double-free when fo goes to same cell	2023-07-10 20:08:48 +09:00
Stefan Holst	ec5626b8ca	remove old connections in substitute node reuse	2023-07-10 09:00:31 +09:00
Stefan Holst	5a693f7b9b	preserve node order during resolve	2023-07-09 23:46:14 +09:00
Stefan Holst	19bbe2c260	update intro	2023-07-09 21:34:01 +09:00
Stefan Holst	d3897246c5	move resolving cells to circuit, more doc	2023-07-09 19:04:22 +09:00
Stefan Holst	9bda7a4c57	capitalize tech libs	2023-07-09 19:01:31 +09:00
Stefan Holst	2270a9eee7	fix fork stripping + fork None values	2023-07-09 19:01:15 +09:00
Stefan Holst	ea45a326ec	add latch, fix xor delays, improve test	2023-07-09 13:42:07 +09:00
Stefan Holst	1e9fe7707b	saed32nm	2023-07-09 00:29:56 +09:00
Stefan Holst	50a5d8a290	one cell inherits name in substitute, sim fix	2023-07-08 22:52:10 +09:00
Stefan Holst	d97555e9e9	fix simprim cells, add saed90	2023-07-08 18:55:52 +09:00
Stefan Holst	47ee8d5878	improve substitute, update notebook output	2023-07-08 18:54:27 +09:00
Stefan Holst	c32584fc76	1to1 fork optimization, fix substitute	2023-07-05 22:55:06 +09:00
Stefan Holst	39b8c1695b	full constants support, fix signal declarations	2023-07-05 22:07:15 +09:00
Stefan Holst	80d26b6f0b	Add AO*211 and OA*211, fix MUX21	2023-07-05 22:01:42 +09:00
Stefan Holst	f7ef78e58d	support for limiting log messages	2023-07-05 21:59:49 +09:00
Stefan Holst	7afb13b33b	mv_str for single values, remove undue assert	2023-07-03 12:40:02 +09:00
Stefan Holst	153442a10a	def file parser	2023-07-03 00:49:23 +09:00
Stefan Holst	afb0a64953	wsa accumulation in wavesim	2023-07-03 00:48:58 +09:00
Stefan Holst	c49667edc1	remove old code, verilog positional pins	2023-06-26 23:23:56 +09:00
Stefan Holst	d921eb5048	sim support for remaining primitives	2023-06-25 22:27:19 +09:00
Stefan Holst	670fb0b3fc	circuit node substitution	2023-06-25 22:26:52 +09:00
Stefan Holst	f8bf579be2	support concat, bus select, ISOL cells	2023-06-24 23:41:08 +09:00
Stefan Holst	f61e2b42e8	support more cells in logic sim	2023-06-24 13:34:35 +09:00
Stefan Holst	4aec335abb	verilog: concat assignments, more comments	2023-06-24 13:33:55 +09:00
Stefan Holst	1a9cb396bf	tweak repr, doc	2023-06-24 13:32:40 +09:00
Stefan Holst	3875dc38f9	docs	2023-06-21 23:23:01 +09:00
Stefan Holst	ecb7171c37	docs	2023-06-21 23:18:17 +09:00
Stefan Holst	8957db48ab	docs	2023-06-20 06:54:59 +09:00
Stefan Holst	0b15f9fa18	doc improvements	2023-06-19 17:05:39 +09:00
Stefan Holst	dc76a9f517	new into demo	2023-06-19 14:01:31 +09:00
Stefan Holst	0968cb451e	docs, fix stil unassigned, fix io_locs for busses	2023-06-19 13:12:17 +09:00
Stefan Holst	947df89434	add AOI21 to logic sim	2023-06-02 00:04:34 +09:00
Stefan Holst	f17e461fdd	fix reading directly from file handle	2023-05-19 14:57:02 +09:00
Stefan Holst	d6d981a351	support for det vars	2023-04-05 18:35:55 +09:00
Stefan Holst	7a060b1831	support for static variations	2023-03-28 11:10:38 +09:00
Stefan Holst	03802ac9f8	make sims pickleable	2023-03-22 13:55:53 +09:00
Stefan Holst	70caea065e	more cleanup	2023-03-20 14:14:06 +09:00
stefan	f04f1b0012	cleanup	2023-03-20 10:31:55 +09:00
Stefan Holst	44b0c887d7	random sampling of delays	2023-03-19 20:30:27 +09:00
Stefan Holst	4e2022291e	fix cuda ppo_to_ppi	2023-03-15 15:15:22 +09:00
Stefan Holst	5566b80e52	simprim, vat refactor, batchrange	2023-03-15 10:37:39 +09:00
stefan	63c0b48537	bump	2023-03-14 18:50:15 +09:00
stefan	6520ee23ef	cleanup and new intro notebook	2023-03-14 17:40:50 +09:00
stefan	1810d40959	pytest work without cuda	2023-03-13 23:18:32 +09:00
Stefan Holst	7430ebb068	jitted logic sim	2023-03-13 23:15:20 +09:00
stefan	89f317b463	better circuit statsu, 2v logic sim	2023-03-13 10:50:44 +09:00
Stefan Holst	753ce566e4	Timer improvements, log in yaml	2023-03-13 10:45:41 +09:00
stefan	1eb8d87884	faster logic sim, removing MVArray, BPArray	2023-03-12 23:59:10 +09:00