Stefan Holst
9f9902c613
remove _static
2023-07-22 16:48:51 +09:00
Stefan Holst
eb4e0f4529
improve readthedocs config
2023-07-22 16:40:57 +09:00
Stefan Holst
821ead0c7a
add readthedocs conf for py3.8
2023-07-22 16:34:57 +09:00
Stefan Holst
351d809306
for release 0.0.4
...
- Circuit: is now pickleable and comparable
- Circuit: utilities for locating/indexing io-ports
- Verilog: parser fixes, support yosys-style verilog
- SDF: parser fixes, full XOR support
- STIL: parser fixes
- Simulators: faster, up to 4-input cells, pickleable
- WaveSim: WSA calculation support
- WaveSim: Per-simulation parameters and delays
- Logic: Data are now raw numpy arrays
- Logic: More tools for bit-packing
- Added DEF parser
- Better techlib support for NanGate, SAED, GSC180
- Tests and docs improvements
2023-07-22 16:13:01 +09:00
Stefan Holst
0ade89defa
remove old test data, intro check
2023-07-22 15:58:16 +09:00
Stefan Holst
7f4026f504
def-file docs
2023-07-22 15:52:51 +09:00
Stefan Holst
e6a0d59d44
def-file docs
2023-07-22 15:52:28 +09:00
Stefan Holst
63e5f32e21
better ignore
2023-07-22 13:24:25 +09:00
Stefan Holst
35e727e714
better docs, new techlib as default, fix tests
2023-07-22 13:11:11 +09:00
Stefan Holst
83445e2bbd
support for newer NANGATE lib
2023-07-21 22:14:29 +09:00
Stefan Holst
c67148c0ee
doc fix
2023-07-21 22:13:25 +09:00
Stefan Holst
280c425486
fix test
2023-07-12 22:35:53 +09:00
Stefan Holst
5be82da49a
avoid holes in forks, update intro
2023-07-12 22:32:22 +09:00
Stefan Holst
b3dbe9765a
fix xor in libs, remove old code
2023-07-12 21:10:27 +09:00
Stefan Holst
5e573b0408
fix substitute for inputs with fo, dot graph
2023-07-12 21:06:16 +09:00
Stefan Holst
08d9f5a9bf
one-bit busses
2023-07-12 16:32:08 +09:00
Stefan Holst
b098fb219d
fix for unconnected named pins, double-declaration
2023-07-12 11:36:43 +09:00
Stefan Holst
97387e962b
add GSC180nm
2023-07-12 11:35:15 +09:00
Stefan Holst
f4d875f7e5
docs
2023-07-12 11:34:45 +09:00
Stefan Holst
cf9a98b5ce
del deprecated sdf code, explicit tlib use
2023-07-10 20:35:19 +09:00
Stefan Holst
d8f605a47a
fix double-free when fo goes to same cell
2023-07-10 20:08:48 +09:00
Stefan Holst
ec5626b8ca
remove old connections in substitute node reuse
2023-07-10 09:00:31 +09:00
Stefan Holst
5a693f7b9b
preserve node order during resolve
2023-07-09 23:46:14 +09:00
Stefan Holst
19bbe2c260
update intro
2023-07-09 21:34:01 +09:00
Stefan Holst
d3897246c5
move resolving cells to circuit, more doc
2023-07-09 19:04:22 +09:00
Stefan Holst
9bda7a4c57
capitalize tech libs
2023-07-09 19:01:31 +09:00
Stefan Holst
2270a9eee7
fix fork stripping + fork None values
2023-07-09 19:01:15 +09:00
Stefan Holst
ea45a326ec
add latch, fix xor delays, improve test
2023-07-09 13:42:07 +09:00
Stefan Holst
1e9fe7707b
saed32nm
2023-07-09 00:29:56 +09:00
Stefan Holst
50a5d8a290
one cell inherits name in substitute, sim fix
2023-07-08 22:52:10 +09:00
Stefan Holst
d97555e9e9
fix simprim cells, add saed90
2023-07-08 18:55:52 +09:00
Stefan Holst
47ee8d5878
improve substitute, update notebook output
2023-07-08 18:54:27 +09:00
Stefan Holst
c32584fc76
1to1 fork optimization, fix substitute
2023-07-05 22:55:06 +09:00
Stefan Holst
39b8c1695b
full constants support, fix signal declarations
2023-07-05 22:07:15 +09:00
Stefan Holst
80d26b6f0b
Add AO*211 and OA*211, fix MUX21
2023-07-05 22:01:42 +09:00
Stefan Holst
f7ef78e58d
support for limiting log messages
2023-07-05 21:59:49 +09:00
Stefan Holst
7afb13b33b
mv_str for single values, remove undue assert
2023-07-03 12:40:02 +09:00
Stefan Holst
153442a10a
def file parser
2023-07-03 00:49:23 +09:00
Stefan Holst
afb0a64953
wsa accumulation in wavesim
2023-07-03 00:48:58 +09:00
Stefan Holst
c49667edc1
remove old code, verilog positional pins
2023-06-26 23:23:56 +09:00
Stefan Holst
d921eb5048
sim support for remaining primitives
2023-06-25 22:27:19 +09:00
Stefan Holst
670fb0b3fc
circuit node substitution
2023-06-25 22:26:52 +09:00
Stefan Holst
f8bf579be2
support concat, bus select, ISOL cells
2023-06-24 23:41:08 +09:00
Stefan Holst
f61e2b42e8
support more cells in logic sim
2023-06-24 13:34:35 +09:00
Stefan Holst
4aec335abb
verilog: concat assignments, more comments
2023-06-24 13:33:55 +09:00
Stefan Holst
1a9cb396bf
tweak repr, doc
2023-06-24 13:32:40 +09:00
Stefan Holst
3875dc38f9
docs
2023-06-21 23:23:01 +09:00
Stefan Holst
ecb7171c37
docs
2023-06-21 23:18:17 +09:00
Stefan Holst
8957db48ab
docs
2023-06-20 06:54:59 +09:00
Stefan Holst
0b15f9fa18
doc improvements
2023-06-19 17:05:39 +09:00
Stefan Holst