 stefan
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541cccd756
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fix sim model for PO that also drive further logic
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2025-11-23 21:34:58 +09:00 |
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stefan
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dd4e5c861a
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fix sim model generation for circuits with dangling nodes
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2025-11-20 15:28:41 +09:00 |
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stefan
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9cebbcce8f
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support for storing responses separately
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2025-11-11 18:13:08 +09:00 |
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stefan
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09420fd72c
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new logic sim interface prototype, simprim lib and test
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2025-11-02 20:56:14 +09:00 |
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stefan
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5bcc1c1d77
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new synthetic techlib with kyupy simprims
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2025-11-02 20:49:37 +09:00 |
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stefan
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df8a58f57b
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generate proper simprims in bench parser
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2025-11-02 20:44:04 +09:00 |
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stefan
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3dfd0cb60d
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euivalence test, op format doc
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2025-10-31 17:13:58 +09:00 |
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stefan
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21439e3595
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circuit objects and nodes/lines of different circuits are not quivalent.
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2025-10-31 17:12:50 +09:00 |
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stefan
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88a5c79161
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dot fix and updated intro nb
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2025-10-23 22:48:18 +09:00 |
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stefan
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9ca437fe47
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fault injection for 4v sim, wave_sim test fix
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2025-10-23 21:26:52 +09:00 |
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stefan
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0cdaf71963
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fix for latest lark
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2025-10-23 21:25:50 +09:00 |
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stefan
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75972d7bb2
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numba config deprecated
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2025-10-23 21:25:36 +09:00 |
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stefan
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469dc18aa9
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lark dependency update
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2025-10-23 18:20:29 +09:00 |
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stefan
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674f3dea4a
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Merge branch 'main' into devel
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2025-06-23 16:06:02 +09:00 |
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stefan
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55d62ff354
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sphinx config
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2025-06-23 15:54:31 +09:00 |
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stefan
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e311b1098a
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sphinx config
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2025-06-23 15:45:35 +09:00 |
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stefan
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aea633ac8d
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for release 0.0.5
* Techlib: fix NanGate variants
* Circuit: more visitor and manipulator utilities
* mv_transition: produce stable values when arguments are UNASSIGNED
* Verilog: better assign processing
* STIL parsing improvements
* SDF: conditional parsing (semantics ignored for now), better interconnect annotation, more robust name matching
* sim: use ALAP topo-sort
* logic_sim: improved fault injection, faster 6V sim
* wave_sim: use correct thresholds for pulse filtering, partial delta-sim support, per-sim delay factor
* log: fix limiter
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2025-06-23 15:39:55 +09:00 |
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stefan
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187d176cfd
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partial ternary if support
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2025-06-02 12:20:42 +09:00 |
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stefan
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ba1de0bea9
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support for per-simulation delay factors
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2025-01-17 13:17:44 +09:00 |
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stefan
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5769aa3716
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deactivate delta sim
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2025-01-17 11:28:12 +09:00 |
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stefan
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e97c370d39
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support stuck-at fault model injection for 2-valued logic sim
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2024-12-06 13:42:22 +09:00 |
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stefan
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3b7106be80
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fix deferred assignments
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2024-11-07 17:06:00 +09:00 |
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stefan
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d2357859f6
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more robust matching and assign processing
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2024-04-15 17:01:11 +09:00 |
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stefan
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53629c5c28
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support injection into specific sims
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2024-04-12 15:23:54 +09:00 |
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stefan
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e64845e8c0
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fanout generator
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2024-04-10 19:28:32 +09:00 |
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stefan
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da98ca2db7
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signal flips in compiled code
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2024-04-10 19:27:06 +09:00 |
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stefan
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deb4599206
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fix tests
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2024-04-08 23:21:24 +09:00 |
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stefan
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c1c9ec9aae
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pin_name, cleanup legacy code
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2024-04-08 16:35:21 +09:00 |
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stefan
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4c55dcec60
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delta sim for improving fault sim performance
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2024-04-08 00:29:12 +09:00 |
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stefan
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a4b7364478
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mux21 in 6v logic sim, more test fixtures
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2024-04-06 15:22:46 +09:00 |
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stefan
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f59e97afa9
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remove hashes, add lst, overflow, ebuf
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2024-04-05 23:24:00 +09:00 |
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stefan
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f6baf9cb5e
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a fast 6v sim
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2024-04-05 23:21:59 +09:00 |
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stefan
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fc030c6708
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allow interconnect annotations without forks
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2024-04-05 23:21:23 +09:00 |
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