Stefan Holst
469dc18aa9
lark dependency update
6 months ago
stefan
33addab141
fix output with newest numpy
6 months ago
Stefan Holst
674f3dea4a
Merge branch 'main' into devel
10 months ago
Stefan Holst
55d62ff354
sphinx config
10 months ago
Stefan Holst
e311b1098a
sphinx config
10 months ago
Stefan Holst
aea633ac8d
for release 0.0.5
...
* Techlib: fix NanGate variants
* Circuit: more visitor and manipulator utilities
* mv_transition: produce stable values when arguments are UNASSIGNED
* Verilog: better assign processing
* STIL parsing improvements
* SDF: conditional parsing (semantics ignored for now), better interconnect annotation, more robust name matching
* sim: use ALAP topo-sort
* logic_sim: improved fault injection, faster 6V sim
* wave_sim: use correct thresholds for pulse filtering, partial delta-sim support, per-sim delay factor
* log: fix limiter
10 months ago
Stefan Holst
187d176cfd
partial ternary if support
11 months ago
Stefan Holst
ba1de0bea9
support for per-simulation delay factors
1 year ago
Stefan Holst
5769aa3716
deactivate delta sim
1 year ago
Stefan Holst
e97c370d39
support stuck-at fault model injection for 2-valued logic sim
1 year ago
Stefan Holst
3b7106be80
fix deferred assignments
1 year ago
Stefan Holst
d2357859f6
more robust matching and assign processing
2 years ago
Stefan Holst
53629c5c28
support injection into specific sims
2 years ago
Stefan Holst
e64845e8c0
fanout generator
2 years ago
Stefan Holst
da98ca2db7
signal flips in compiled code
2 years ago
Stefan Holst
deb4599206
fix tests
2 years ago
Stefan Holst
c1c9ec9aae
pin_name, cleanup legacy code
2 years ago
Stefan Holst
4c55dcec60
delta sim for improving fault sim performance
2 years ago
Stefan Holst
a4b7364478
mux21 in 6v logic sim, more test fixtures
2 years ago
Stefan Holst
f59e97afa9
remove hashes, add lst, overflow, ebuf
2 years ago
Stefan Holst
f6baf9cb5e
a fast 6v sim
2 years ago
Stefan Holst
fc030c6708
allow interconnect annotations without forks
2 years ago
795cac0716
initial and final values from mvarrays
2 years ago
3a8777e0a3
none-filtering iterator for GrowingList
2 years ago
68e8cb844a
pass line id to inject_cb
2 years ago
Stefan Holst
1a3b91c1c0
fix comment
2 years ago
aa7536b8b0
line use and diff
2 years ago
fccf5e0d84
fix log limit
2 years ago
a6d1e4099c
alap toposort, improve tests
2 years ago
1654915ed6
support for partial re-sim
2 years ago
d2a2484efa
fix fault injection
2 years ago
de79393dfc
fix log limiter, use eng notation
3 years ago
4bb3f3424a
cond in sdf parser. ignored for now.
3 years ago
a6243b43f6
keep s_nodes
3 years ago
baeb759824
types, perf op growing list, keep s_nodes
3 years ago
967a232b1c
fix pulse threshold selection
3 years ago
8096416b0e
save test position for each pattern
3 years ago
a4cce9f8c0
Produce stable value when trans. to/from -
3 years ago
4f6b733eb4
fix NanGate variants, version bump
3 years ago
371bc906b3
Merge branch 'main' into devel
...
fix readthedocs
3 years ago
9f9902c613
remove _static
3 years ago
eb4e0f4529
improve readthedocs config
3 years ago
821ead0c7a
add readthedocs conf for py3.8
3 years ago
351d809306
for release 0.0.4
...
- Circuit: is now pickleable and comparable
- Circuit: utilities for locating/indexing io-ports
- Verilog: parser fixes, support yosys-style verilog
- SDF: parser fixes, full XOR support
- STIL: parser fixes
- Simulators: faster, up to 4-input cells, pickleable
- WaveSim: WSA calculation support
- WaveSim: Per-simulation parameters and delays
- Logic: Data are now raw numpy arrays
- Logic: More tools for bit-packing
- Added DEF parser
- Better techlib support for NanGate, SAED, GSC180
- Tests and docs improvements
3 years ago
0ade89defa
remove old test data, intro check
3 years ago
7f4026f504
def-file docs
3 years ago
e6a0d59d44
def-file docs
3 years ago
63e5f32e21
better ignore
3 years ago
35e727e714
better docs, new techlib as default, fix tests
3 years ago
83445e2bbd
support for newer NANGATE lib
3 years ago
Stefan Holst
stefan
Stefan Holst