3b7106be80
fix deferred assignments
7 days ago
d2357859f6
more robust matching and assign processing
7 months ago
53629c5c28
support injection into specific sims
7 months ago
e64845e8c0
fanout generator
7 months ago
da98ca2db7
signal flips in compiled code
7 months ago
deb4599206
fix tests
7 months ago
c1c9ec9aae
pin_name, cleanup legacy code
7 months ago
4c55dcec60
delta sim for improving fault sim performance
7 months ago
a4b7364478
mux21 in 6v logic sim, more test fixtures
7 months ago
f59e97afa9
remove hashes, add lst, overflow, ebuf
7 months ago
f6baf9cb5e
a fast 6v sim
7 months ago
fc030c6708
allow interconnect annotations without forks
7 months ago
795cac0716
initial and final values from mvarrays
7 months ago
3a8777e0a3
none-filtering iterator for GrowingList
7 months ago
68e8cb844a
pass line id to inject_cb
9 months ago
Stefan Holst
1a3b91c1c0
fix comment
11 months ago
aa7536b8b0
line use and diff
11 months ago
fccf5e0d84
fix log limit
11 months ago
a6d1e4099c
alap toposort, improve tests
1 year ago
1654915ed6
support for partial re-sim
1 year ago
d2a2484efa
fix fault injection
1 year ago
de79393dfc
fix log limiter, use eng notation
1 year ago
4bb3f3424a
cond in sdf parser. ignored for now.
1 year ago
a6243b43f6
keep s_nodes
1 year ago
baeb759824
types, perf op growing list, keep s_nodes
1 year ago
967a232b1c
fix pulse threshold selection
1 year ago
8096416b0e
save test position for each pattern
1 year ago
a4cce9f8c0
Produce stable value when trans. to/from -
1 year ago
4f6b733eb4
fix NanGate variants, version bump
1 year ago
371bc906b3
Merge branch 'main' into devel
...
fix readthedocs
1 year ago
9f9902c613
remove _static
1 year ago
eb4e0f4529
improve readthedocs config
1 year ago
821ead0c7a
add readthedocs conf for py3.8
1 year ago
351d809306
for release 0.0.4
...
- Circuit: is now pickleable and comparable
- Circuit: utilities for locating/indexing io-ports
- Verilog: parser fixes, support yosys-style verilog
- SDF: parser fixes, full XOR support
- STIL: parser fixes
- Simulators: faster, up to 4-input cells, pickleable
- WaveSim: WSA calculation support
- WaveSim: Per-simulation parameters and delays
- Logic: Data are now raw numpy arrays
- Logic: More tools for bit-packing
- Added DEF parser
- Better techlib support for NanGate, SAED, GSC180
- Tests and docs improvements
1 year ago
0ade89defa
remove old test data, intro check
1 year ago
7f4026f504
def-file docs
1 year ago
e6a0d59d44
def-file docs
1 year ago
63e5f32e21
better ignore
1 year ago
35e727e714
better docs, new techlib as default, fix tests
1 year ago
83445e2bbd
support for newer NANGATE lib
1 year ago
c67148c0ee
doc fix
1 year ago
280c425486
fix test
1 year ago
5be82da49a
avoid holes in forks, update intro
1 year ago
b3dbe9765a
fix xor in libs, remove old code
1 year ago
5e573b0408
fix substitute for inputs with fo, dot graph
1 year ago
08d9f5a9bf
one-bit busses
1 year ago
b098fb219d
fix for unconnected named pins, double-declaration
1 year ago
97387e962b
add GSC180nm
1 year ago
f4d875f7e5
docs
1 year ago
cf9a98b5ce
del deprecated sdf code, explicit tlib use
1 year ago
Stefan Holst
Stefan Holst