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Commit Graph

146 Commits (371bc906b330bf292b1cccb0b6fbe81caba5c0df)

 

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Author	SHA1	Message	Date
Stefan Holst	371bc906b3	Merge branch 'main' into devel ... fix readthedocs	1 year ago
Stefan Holst	9f9902c613	remove _static	1 year ago
Stefan Holst	eb4e0f4529	improve readthedocs config	1 year ago
Stefan Holst	821ead0c7a	add readthedocs conf for py3.8	1 year ago
Stefan Holst	351d809306	for release 0.0.4 ... - Circuit: is now pickleable and comparable - Circuit: utilities for locating/indexing io-ports - Verilog: parser fixes, support yosys-style verilog - SDF: parser fixes, full XOR support - STIL: parser fixes - Simulators: faster, up to 4-input cells, pickleable - WaveSim: WSA calculation support - WaveSim: Per-simulation parameters and delays - Logic: Data are now raw numpy arrays - Logic: More tools for bit-packing - Added DEF parser - Better techlib support for NanGate, SAED, GSC180 - Tests and docs improvements	1 year ago
Stefan Holst	0ade89defa	remove old test data, intro check	1 year ago
Stefan Holst	7f4026f504	def-file docs	1 year ago
Stefan Holst	e6a0d59d44	def-file docs	1 year ago
Stefan Holst	63e5f32e21	better ignore	1 year ago
Stefan Holst	35e727e714	better docs, new techlib as default, fix tests	1 year ago
Stefan Holst	83445e2bbd	support for newer NANGATE lib	1 year ago
Stefan Holst	c67148c0ee	doc fix	1 year ago
Stefan Holst	280c425486	fix test	1 year ago
Stefan Holst	5be82da49a	avoid holes in forks, update intro	1 year ago
Stefan Holst	b3dbe9765a	fix xor in libs, remove old code	1 year ago
Stefan Holst	5e573b0408	fix substitute for inputs with fo, dot graph	1 year ago
Stefan Holst	08d9f5a9bf	one-bit busses	1 year ago
Stefan Holst	b098fb219d	fix for unconnected named pins, double-declaration	1 year ago
Stefan Holst	97387e962b	add GSC180nm	1 year ago
Stefan Holst	f4d875f7e5	docs	1 year ago
Stefan Holst	cf9a98b5ce	del deprecated sdf code, explicit tlib use	1 year ago
Stefan Holst	d8f605a47a	fix double-free when fo goes to same cell	1 year ago
Stefan Holst	ec5626b8ca	remove old connections in substitute node reuse	1 year ago
Stefan Holst	5a693f7b9b	preserve node order during resolve	1 year ago
Stefan Holst	19bbe2c260	update intro	1 year ago
Stefan Holst	d3897246c5	move resolving cells to circuit, more doc	1 year ago
Stefan Holst	9bda7a4c57	capitalize tech libs	1 year ago
Stefan Holst	2270a9eee7	fix fork stripping + fork None values	1 year ago
Stefan Holst	ea45a326ec	add latch, fix xor delays, improve test	1 year ago
Stefan Holst	1e9fe7707b	saed32nm	1 year ago
Stefan Holst	50a5d8a290	one cell inherits name in substitute, sim fix	1 year ago
Stefan Holst	d97555e9e9	fix simprim cells, add saed90	1 year ago
Stefan Holst	47ee8d5878	improve substitute, update notebook output	1 year ago
Stefan Holst	c32584fc76	1to1 fork optimization, fix substitute	1 year ago
Stefan Holst	39b8c1695b	full constants support, fix signal declarations	1 year ago
Stefan Holst	80d26b6f0b	Add AO*211 and OA*211, fix MUX21	1 year ago
Stefan Holst	f7ef78e58d	support for limiting log messages	1 year ago
Stefan Holst	7afb13b33b	mv_str for single values, remove undue assert	1 year ago
Stefan Holst	153442a10a	def file parser	2 years ago
Stefan Holst	afb0a64953	wsa accumulation in wavesim	2 years ago
Stefan Holst	c49667edc1	remove old code, verilog positional pins	2 years ago
Stefan Holst	d921eb5048	sim support for remaining primitives	2 years ago
Stefan Holst	670fb0b3fc	circuit node substitution	2 years ago
Stefan Holst	f8bf579be2	support concat, bus select, ISOL cells	2 years ago
Stefan Holst	f61e2b42e8	support more cells in logic sim	2 years ago
Stefan Holst	4aec335abb	verilog: concat assignments, more comments	2 years ago
Stefan Holst	1a9cb396bf	tweak repr, doc	2 years ago
Stefan Holst	3875dc38f9	docs	2 years ago
Stefan Holst	ecb7171c37	docs	2 years ago
Stefan Holst	8957db48ab	docs	2 years ago