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devel
Stefan Holst 3 years ago
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commit
8bbaaf8fae
  1. 4
      src/kyupy/stil.py

4
src/kyupy/stil.py

@ -103,8 +103,8 @@ class StilFile:
"""Assembles and returns a LoC scan test pattern set for given circuit. """Assembles and returns a LoC scan test pattern set for given circuit.
This function assumes a launch-on-capture (LoC) delay test. This function assumes a launch-on-capture (LoC) delay test.
It performs a logic simulation to obtain the first capture pattern (the one that launches the It performs a logic simulation to obtain the first capture pattern (the one that launches the delay
delay test) and assembles the test pattern set from from pairs for initialization- and launch-patterns. test) and assembles the test pattern set from from pairs for initialization- and launch-patterns.
""" """
interface, pi_map, po_map, scan_maps, scan_inversions = self._maps(circuit) interface, pi_map, po_map, scan_maps, scan_inversions = self._maps(circuit)
init = logic.MVArray((len(interface), len(self.patterns)), m=4) init = logic.MVArray((len(interface), len(self.patterns)), m=4)

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