diff --git a/src/kyupy/stil.py b/src/kyupy/stil.py
index a4fa2d6..fe714cb 100644
--- a/src/kyupy/stil.py
+++ b/src/kyupy/stil.py
@@ -103,8 +103,8 @@ class StilFile:
         """Assembles and returns a LoC scan test pattern set for given circuit.
 
         This function assumes a launch-on-capture (LoC) delay test.
-        It performs a logic simulation to obtain the first capture pattern (the one that launches the
-        delay test) and assembles the test pattern set from from pairs for initialization- and launch-patterns.
+        It performs a logic simulation to obtain the first capture pattern (the one that launches the delay
+        test) and assembles the test pattern set from from pairs for initialization- and launch-patterns.
         """
         interface, pi_map, po_map, scan_maps, scan_inversions = self._maps(circuit)
         init = logic.MVArray((len(interface), len(self.patterns)), m=4)