From 8bbaaf8faefea9d5c3922e162e82f7787e7bb4bd Mon Sep 17 00:00:00 2001 From: Stefan Holst Date: Mon, 26 Jul 2021 10:52:33 +0900 Subject: [PATCH] comment change --- src/kyupy/stil.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/kyupy/stil.py b/src/kyupy/stil.py index a4fa2d6..fe714cb 100644 --- a/src/kyupy/stil.py +++ b/src/kyupy/stil.py @@ -103,8 +103,8 @@ class StilFile: """Assembles and returns a LoC scan test pattern set for given circuit. This function assumes a launch-on-capture (LoC) delay test. - It performs a logic simulation to obtain the first capture pattern (the one that launches the - delay test) and assembles the test pattern set from from pairs for initialization- and launch-patterns. + It performs a logic simulation to obtain the first capture pattern (the one that launches the delay + test) and assembles the test pattern set from from pairs for initialization- and launch-patterns. """ interface, pi_map, po_map, scan_maps, scan_inversions = self._maps(circuit) init = logic.MVArray((len(interface), len(self.patterns)), m=4)