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  • 08d9f5a9bf one-bit busses Stefan Holst 2023-07-12 16:32:08 +0900
  • b098fb219d fix for unconnected named pins, double-declaration Stefan Holst 2023-07-12 11:36:43 +0900
  • 97387e962b add GSC180nm Stefan Holst 2023-07-12 11:35:15 +0900
  • f4d875f7e5 docs Stefan Holst 2023-07-12 11:34:45 +0900
  • cf9a98b5ce del deprecated sdf code, explicit tlib use Stefan Holst 2023-07-10 20:35:19 +0900
  • d8f605a47a fix double-free when fo goes to same cell Stefan Holst 2023-07-10 20:08:48 +0900
  • ec5626b8ca remove old connections in substitute node reuse Stefan Holst 2023-07-10 09:00:31 +0900
  • 5a693f7b9b preserve node order during resolve Stefan Holst 2023-07-09 23:46:14 +0900
  • 19bbe2c260 update intro Stefan Holst 2023-07-09 21:34:01 +0900
  • d3897246c5 move resolving cells to circuit, more doc Stefan Holst 2023-07-09 19:04:22 +0900
  • 9bda7a4c57 capitalize tech libs Stefan Holst 2023-07-09 19:01:31 +0900
  • 2270a9eee7 fix fork stripping + fork None values Stefan Holst 2023-07-09 19:01:15 +0900
  • ea45a326ec add latch, fix xor delays, improve test Stefan Holst 2023-07-09 13:42:07 +0900
  • 1e9fe7707b saed32nm Stefan Holst 2023-07-09 00:29:56 +0900
  • 50a5d8a290 one cell inherits name in substitute, sim fix Stefan Holst 2023-07-08 22:52:10 +0900
  • d97555e9e9 fix simprim cells, add saed90 Stefan Holst 2023-07-08 18:55:52 +0900
  • 47ee8d5878 improve substitute, update notebook output Stefan Holst 2023-07-08 18:54:27 +0900
  • c32584fc76 1to1 fork optimization, fix substitute Stefan Holst 2023-07-05 22:55:06 +0900
  • 39b8c1695b full constants support, fix signal declarations Stefan Holst 2023-07-05 22:07:15 +0900
  • 80d26b6f0b Add AO*211 and OA*211, fix MUX21 Stefan Holst 2023-07-05 22:01:42 +0900
  • f7ef78e58d support for limiting log messages Stefan Holst 2023-07-05 21:59:49 +0900
  • 7afb13b33b mv_str for single values, remove undue assert Stefan Holst 2023-07-03 12:40:02 +0900
  • 153442a10a def file parser Stefan Holst 2023-07-03 00:49:23 +0900
  • afb0a64953 wsa accumulation in wavesim Stefan Holst 2023-07-03 00:48:58 +0900
  • c49667edc1 remove old code, verilog positional pins Stefan Holst 2023-06-26 23:23:56 +0900
  • d921eb5048 sim support for remaining primitives Stefan Holst 2023-06-25 22:27:19 +0900
  • 670fb0b3fc circuit node substitution Stefan Holst 2023-06-25 22:26:52 +0900
  • f8bf579be2 support concat, bus select, ISOL cells Stefan Holst 2023-06-24 23:41:08 +0900
  • f61e2b42e8 support more cells in logic sim Stefan Holst 2023-06-24 13:34:35 +0900
  • 4aec335abb verilog: concat assignments, more comments Stefan Holst 2023-06-24 13:33:55 +0900
  • 1a9cb396bf tweak repr, doc Stefan Holst 2023-06-24 13:32:40 +0900
  • 3875dc38f9 docs Stefan Holst 2023-06-21 23:23:01 +0900
  • ecb7171c37 docs Stefan Holst 2023-06-21 23:18:17 +0900
  • 8957db48ab docs Stefan Holst 2023-06-20 06:54:59 +0900
  • 0b15f9fa18 doc improvements Stefan Holst 2023-06-19 17:05:39 +0900
  • dc76a9f517 new into demo Stefan Holst 2023-06-19 14:01:31 +0900
  • 0968cb451e docs, fix stil unassigned, fix io_locs for busses Stefan Holst 2023-06-19 13:12:17 +0900
  • 947df89434 add AOI21 to logic sim Stefan Holst 2023-06-02 00:04:34 +0900
  • f17e461fdd fix reading directly from file handle Stefan Holst 2023-05-19 14:57:02 +0900
  • d6d981a351 support for det vars Stefan Holst 2023-04-05 18:35:55 +0900
  • 7a060b1831 support for static variations Stefan Holst 2023-03-28 11:10:38 +0900
  • 03802ac9f8 make sims pickleable Stefan Holst 2023-03-22 13:55:53 +0900
  • 70caea065e more cleanup Stefan Holst 2023-03-20 14:14:06 +0900
  • f04f1b0012 cleanup Stefan Holst 2023-03-20 10:31:55 +0900
  • 44b0c887d7 random sampling of delays Stefan Holst 2023-03-19 20:30:27 +0900
  • 4e2022291e fix cuda ppo_to_ppi Stefan Holst 2023-03-15 15:15:22 +0900
  • 5566b80e52 simprim, vat refactor, batchrange Stefan Holst 2023-03-15 10:37:39 +0900
  • 63c0b48537 bump stefan 2023-03-14 18:50:15 +0900
  • 6520ee23ef cleanup and new intro notebook stefan 2023-03-14 17:40:50 +0900
  • 1810d40959 pytest work without cuda stefan 2023-03-13 23:18:32 +0900
  • 7430ebb068 jitted logic sim Stefan Holst 2023-03-13 23:15:20 +0900
  • 89f317b463 better circuit statsu, 2v logic sim stefan 2023-03-13 10:48:37 +0900
  • 753ce566e4 Timer improvements, log in yaml Stefan Holst 2023-03-06 23:20:41 +0900
  • 1eb8d87884 faster logic sim, removing MVArray, BPArray stefan 2023-03-12 23:59:10 +0900
  • 02f3a0e1b2 correct timing padding Stefan Holst 2023-02-28 09:39:01 +0900
  • fc8e65e788 bit-packing utility Stefan Holst 2023-02-28 09:38:28 +0900
  • d80a3ae2b1 timer utility Stefan Holst 2023-02-28 09:38:02 +0900
  • 7bfc02e683 more on-gpu code, bump python requirement Stefan Holst 2023-02-26 22:37:15 +0900
  • 8da4a62bce switch to new wave_sim, silence occupancy warnings Stefan Holst 2023-02-26 13:54:01 +0900
  • 3497bfdc75 first gpu-code, cached test fixtures Stefan Holst 2023-02-26 13:09:49 +0900
  • f1ebe1487c new wave sim Stefan Holst 2023-02-26 11:04:38 +0900
  • f0dac36ac7 interface -> io_nodes, io_loc fix Stefan Holst 2023-02-24 21:56:29 +0900
  • b2953aef25 only dff Stefan Holst 2023-02-22 13:37:15 +0900
  • 3774b14286 support ppi/ppo Stefan Holst 2023-02-22 13:32:49 +0900
  • 4847ad9c40 locating io ports and busses by name Stefan Holst 2023-02-21 23:26:48 +0900
  • 6801606dca new common scheduler for simulators Stefan Holst 2023-02-21 19:27:54 +0900
  • faf41f0863 ff transitions switch Stefan Holst 2023-02-06 09:53:44 +0900
  • 6430f10f73 HADD pin index fix Stefan Holst 2023-02-06 09:52:32 +0900
  • fa19af8c31 4-input gate simulator Stefan Holst 2023-01-18 14:34:17 +0900
  • 93a0858d2f oai and aoi pin handling fix Stefan Holst 2023-01-16 17:37:41 +0900
  • 1f2808ee31 Merge branch 'main' into devel Stefan Holst 2022-07-21 22:10:20 +0900
  • 840b816804 Circuit pickle, STIL/SDF/techlib fixes, sdata - fix pin indices for various SC lib variants - SDF annotation improvements - STIL loading improvements - Support for per-simulation parameters in WaveSim - Circuit is now pickleable and comparable Stefan Holst 2022-07-21 22:01:51 +0900
  • 163b348a0c year bump Stefan Holst 2022-07-21 18:47:25 +0900
  • ecfc692edc support reset RN for scan cells Stefan Holst 2022-07-21 17:16:35 +0900
  • afb7e745a1 adding aoi to logic sim Stefan Holst 2022-07-21 17:15:55 +0900
  • 6a8841c3c6 revert wave_eval4 Stefan Holst 2022-07-21 16:57:20 +0900
  • c530983afa accept I as a first input Stefan Holst 2022-03-17 14:57:37 +0900
  • 775b13c694 fix off-by-1 pin index when loading AOI and OAI cells Stefan Holst 2022-02-02 15:05:14 +0900
  • 584445f3b1 wave eval for 4-input gates Stefan Holst 2021-11-22 14:54:38 +0900
  • 85dd02d4d7 interpret N as unassigned in STIL Stefan Holst 2021-11-07 18:51:41 +0900
  • 7c03271048 improve robustness of sdf annotation and wave sim Stefan Holst 2021-09-01 12:57:55 +0900
  • 8bbaaf8fae comment change Stefan Holst 2021-07-26 10:52:33 +0900
  • d59d6401c8 fix stil loading and logic sim capture Stefan Holst 2021-07-22 17:21:58 +0900
  • 387c436207 fix tests, version bump Stefan Holst 2021-07-19 14:14:35 +0900
  • b981b1153c add sdata to control individual sims Stefan Holst 2021-06-17 12:05:55 +0900
  • 87d93afb44 fix time in unpickled log objects Stefan Holst 2021-03-31 11:11:25 +0900
  • c3e4090f31 make nodes and lines hashable again Stefan Holst 2021-03-28 19:44:19 +0900
  • 0251d66d28 make circuit pickable and comparable Stefan Holst 2021-03-28 19:35:19 +0900
  • 864230b883 initial letch support, fix capture in logic sim Stefan Holst 2021-03-25 10:36:55 +0900
  • d05841a6a2 Merge branch 'main' into devel Stefan Holst 2021-01-31 18:32:14 +0900
  • b17ab2d148 fixes for IWLS benchmark netlists and older STIL files Stefan Holst 2021-01-31 18:28:56 +0900
  • c5be32d7e5 doc and indent fix Stefan Holst 2021-01-31 18:25:09 +0900
  • 8434f5e694 fixes for IWLS benchmark netlists Stefan Holst 2021-01-31 16:39:47 +0900
  • 9ff2369a55 fix parsing older stil files Stefan Holst 2021-01-31 13:43:03 +0900
  • 82a53e0171 improve techlib for gsclib, better constant handling in verilog parser Stefan Holst 2021-01-31 13:41:36 +0900
  • a2df0e5682 fix ff annotation Stefan Holst 2021-01-22 18:03:18 +0900
  • ec37e11fef Merge branch 'main' into devel Stefan Holst 2021-01-16 14:56:36 +0900
  • c9445f2d79 Docs, __index__, fault injection and TechLib v0.0.3 Stefan Holst 2021-01-16 14:48:27 +0900
  • 3a5a3c128b year bump Stefan Holst 2021-01-16 13:52:18 +0900
  • ee30898cef docs for numba and cuda Stefan Holst 2021-01-16 13:35:20 +0900