bda89dc1b0
support for simple text-based pattern format
2 months ago
8aa0f09254
logic_sim: better docs, deprecate LogicSim, move tests to newer classes
2 months ago
c1ea05555e
fix verilog tests
2 months ago
3a2cfb7788
techlib decides on cell type comb/dff/latch
2 months ago
Stefan Holst
a28128830d
beginning simple always block parsing in verilog
9 months ago
Stefan Holst
fed66f85cb
fix oob in test
9 months ago
Stefan Holst
dd4e5c861a
fix sim model generation for circuits with dangling nodes
9 months ago
31434cfd51
4v sim, fixed 6v sim, better testing
9 months ago
Stefan Holst
09420fd72c
new logic sim interface prototype, simprim lib and test
10 months ago
Stefan Holst
3dfd0cb60d
euivalence test, op format doc
10 months ago
Stefan Holst
9ca437fe47
fault injection for 4v sim, wave_sim test fix
10 months ago
Stefan Holst
aea633ac8d
for release 0.0.5
...
* Techlib: fix NanGate variants
* Circuit: more visitor and manipulator utilities
* mv_transition: produce stable values when arguments are UNASSIGNED
* Verilog: better assign processing
* STIL parsing improvements
* SDF: conditional parsing (semantics ignored for now), better interconnect annotation, more robust name matching
* sim: use ALAP topo-sort
* logic_sim: improved fault injection, faster 6V sim
* wave_sim: use correct thresholds for pulse filtering, partial delta-sim support, per-sim delay factor
* log: fix limiter
1 year ago
Stefan Holst
deb4599206
fix tests
2 years ago
Stefan Holst
a4b7364478
mux21 in 6v logic sim, more test fixtures
2 years ago
Stefan Holst
f6baf9cb5e
a fast 6v sim
2 years ago
Stefan Holst
1a3b91c1c0
fix comment
3 years ago
aa7536b8b0
line use and diff
3 years ago
a6d1e4099c
alap toposort, improve tests
3 years ago
4bb3f3424a
cond in sdf parser. ignored for now.
3 years ago
baeb759824
types, perf op growing list, keep s_nodes
3 years ago
967a232b1c
fix pulse threshold selection
3 years ago
351d809306
for release 0.0.4
...
- Circuit: is now pickleable and comparable
- Circuit: utilities for locating/indexing io-ports
- Verilog: parser fixes, support yosys-style verilog
- SDF: parser fixes, full XOR support
- STIL: parser fixes
- Simulators: faster, up to 4-input cells, pickleable
- WaveSim: WSA calculation support
- WaveSim: Per-simulation parameters and delays
- Logic: Data are now raw numpy arrays
- Logic: More tools for bit-packing
- Added DEF parser
- Better techlib support for NanGate, SAED, GSC180
- Tests and docs improvements
3 years ago
0ade89defa
remove old test data, intro check
3 years ago
35e727e714
better docs, new techlib as default, fix tests
3 years ago
280c425486
fix test
3 years ago
cf9a98b5ce
del deprecated sdf code, explicit tlib use
3 years ago
5a693f7b9b
preserve node order during resolve
3 years ago
ea45a326ec
add latch, fix xor delays, improve test
3 years ago
d97555e9e9
fix simprim cells, add saed90
3 years ago
afb0a64953
wsa accumulation in wavesim
3 years ago
670fb0b3fc
circuit node substitution
3 years ago
f8bf579be2
support concat, bus select, ISOL cells
3 years ago
f61e2b42e8
support more cells in logic sim
3 years ago
0b15f9fa18
doc improvements
3 years ago
dc76a9f517
new into demo
3 years ago
7a060b1831
support for static variations
3 years ago
44b0c887d7
random sampling of delays
3 years ago
5566b80e52
simprim, vat refactor, batchrange
3 years ago
1eb8d87884
faster logic sim, removing MVArray, BPArray
3 years ago
8da4a62bce
switch to new wave_sim, silence occupancy warnings
4 years ago
Stefan Holst
3497bfdc75
first gpu-code, cached test fixtures
4 years ago
Stefan Holst
f1ebe1487c
new wave sim
4 years ago
Stefan Holst
f0dac36ac7
interface -> io_nodes, io_loc fix
4 years ago
840b816804
Circuit pickle, STIL/SDF/techlib fixes, sdata
...
- fix pin indices for various SC lib variants
- SDF annotation improvements
- STIL loading improvements
- Support for per-simulation parameters in WaveSim
- Circuit is now pickleable and comparable
4 years ago
d59d6401c8
fix stil loading and logic sim capture
5 years ago
387c436207
fix tests, version bump
5 years ago
0251d66d28
make circuit pickable and comparable
5 years ago
864230b883
initial letch support, fix capture in logic sim
5 years ago
c9445f2d79
Docs, __index__, fault injection and TechLib
...
- Documentation improvements
- Node and Line objects now provide __index__
- LogicSim cleanup and improvements (inject_cb, cycle, ...)
- Introduce TechLib class to organize tech-specific info
- More human-readable output
- De-linting
6 years ago
62cf56e98a
TechLib class, remove unnecessary .index
6 years ago
stefan
Stefan Holst
Stefan Holst