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Commit Graph

8 Commits (d3897246c59d0f441c33327168962aafd520fef6)

Author	SHA1	Message	Date
Stefan Holst	d97555e9e9	fix simprim cells, add saed90	1 year ago
stefan	1eb8d87884	faster logic sim, removing MVArray, BPArray	2 years ago
Stefan Holst	840b816804	Circuit pickle, STIL/SDF/techlib fixes, sdata ... - fix pin indices for various SC lib variants - SDF annotation improvements - STIL loading improvements - Support for per-simulation parameters in WaveSim - Circuit is now pickleable and comparable	2 years ago
Stefan Holst	d59d6401c8	fix stil loading and logic sim capture	3 years ago
Stefan Holst	864230b883	initial letch support, fix capture in logic sim	4 years ago
Stefan Holst	c9445f2d79	Docs, __index__, fault injection and TechLib ... - Documentation improvements - Node and Line objects now provide __index__ - LogicSim cleanup and improvements (inject_cb, cycle, ...) - Introduce TechLib class to organize tech-specific info - More human-readable output - De-linting	4 years ago
Stefan Holst	ff4de6d782	de-lint and repr improvements	4 years ago
Stefan Holst	64e1de396f	New m-valued logic arrays, documentation, 0.0.2 ... - MVArray for multi-valued logic - BPArray for bit-parallel storage layout - Started documenting with Sphinx - Migrated simulators to new BPArray	4 years ago
Stefan Holst	7f035c1ac5	Migration to new logic value representation	4 years ago
Stefan Holst	7bcfbf502b	Documentation, cleanup, multi-valued logic	4 years ago
Stefan Holst	0c5a7f56e1	Project Import	4 years ago