Stefan Holst
|
d3897246c5
|
move resolving cells to circuit, more doc
|
1 year ago |
|
Stefan Holst
|
9bda7a4c57
|
capitalize tech libs
|
1 year ago |
|
Stefan Holst
|
2270a9eee7
|
fix fork stripping + fork None values
|
1 year ago |
|
Stefan Holst
|
ea45a326ec
|
add latch, fix xor delays, improve test
|
1 year ago |
|
Stefan Holst
|
1e9fe7707b
|
saed32nm
|
1 year ago |
|
Stefan Holst
|
50a5d8a290
|
one cell inherits name in substitute, sim fix
|
1 year ago |
|
Stefan Holst
|
d97555e9e9
|
fix simprim cells, add saed90
|
1 year ago |
|
Stefan Holst
|
47ee8d5878
|
improve substitute, update notebook output
|
1 year ago |
|
Stefan Holst
|
c32584fc76
|
1to1 fork optimization, fix substitute
|
1 year ago |
|
Stefan Holst
|
39b8c1695b
|
full constants support, fix signal declarations
|
1 year ago |
|
Stefan Holst
|
80d26b6f0b
|
Add AO*211 and OA*211, fix MUX21
|
1 year ago |
|
Stefan Holst
|
f7ef78e58d
|
support for limiting log messages
|
1 year ago |
|
Stefan Holst
|
7afb13b33b
|
mv_str for single values, remove undue assert
|
1 year ago |
|
Stefan Holst
|
153442a10a
|
def file parser
|
1 year ago |
|
Stefan Holst
|
afb0a64953
|
wsa accumulation in wavesim
|
1 year ago |
|
Stefan Holst
|
c49667edc1
|
remove old code, verilog positional pins
|
2 years ago |
|
Stefan Holst
|
d921eb5048
|
sim support for remaining primitives
|
2 years ago |
|
Stefan Holst
|
670fb0b3fc
|
circuit node substitution
|
2 years ago |
|
Stefan Holst
|
f8bf579be2
|
support concat, bus select, ISOL cells
|
2 years ago |
|
Stefan Holst
|
f61e2b42e8
|
support more cells in logic sim
|
2 years ago |
|
Stefan Holst
|
4aec335abb
|
verilog: concat assignments, more comments
|
2 years ago |
|
Stefan Holst
|
1a9cb396bf
|
tweak repr, doc
|
2 years ago |
|
Stefan Holst
|
3875dc38f9
|
docs
|
2 years ago |
|
Stefan Holst
|
ecb7171c37
|
docs
|
2 years ago |
|
Stefan Holst
|
8957db48ab
|
docs
|
2 years ago |
|
Stefan Holst
|
0b15f9fa18
|
doc improvements
|
2 years ago |
|
Stefan Holst
|
dc76a9f517
|
new into demo
|
2 years ago |
|
Stefan Holst
|
0968cb451e
|
docs, fix stil unassigned, fix io_locs for busses
|
2 years ago |
|
Stefan Holst
|
947df89434
|
add AOI21 to logic sim
|
2 years ago |
|
Stefan Holst
|
f17e461fdd
|
fix reading directly from file handle
|
2 years ago |
|
Stefan Holst
|
d6d981a351
|
support for det vars
|
2 years ago |
|
Stefan Holst
|
7a060b1831
|
support for static variations
|
2 years ago |
|
Stefan Holst
|
03802ac9f8
|
make sims pickleable
|
2 years ago |
|
Stefan Holst
|
70caea065e
|
more cleanup
|
2 years ago |
|
Stefan Holst
|
f04f1b0012
|
cleanup
|
2 years ago |
|
Stefan Holst
|
44b0c887d7
|
random sampling of delays
|
2 years ago |
|
Stefan Holst
|
4e2022291e
|
fix cuda ppo_to_ppi
|
2 years ago |
|
Stefan Holst
|
5566b80e52
|
simprim, vat refactor, batchrange
|
2 years ago |
 stefan
|
63c0b48537
|
bump
|
2 years ago |
|
stefan
|
6520ee23ef
|
cleanup and new intro notebook
|
2 years ago |
|
stefan
|
1810d40959
|
pytest work without cuda
|
2 years ago |
|
Stefan Holst
|
7430ebb068
|
jitted logic sim
|
2 years ago |
|
stefan
|
89f317b463
|
better circuit statsu, 2v logic sim
|
2 years ago |
|
Stefan Holst
|
753ce566e4
|
Timer improvements, log in yaml
|
2 years ago |
|
stefan
|
1eb8d87884
|
faster logic sim, removing MVArray, BPArray
|
2 years ago |
|
Stefan Holst
|
02f3a0e1b2
|
correct timing padding
|
2 years ago |
|
Stefan Holst
|
fc8e65e788
|
bit-packing utility
|
2 years ago |
|
Stefan Holst
|
d80a3ae2b1
|
timer utility
|
2 years ago |
|
Stefan Holst
|
7bfc02e683
|
more on-gpu code, bump python requirement
|
2 years ago |
|
Stefan Holst
|
8da4a62bce
|
switch to new wave_sim, silence occupancy warnings
|
2 years ago |
