a4b7364478
mux21 in 6v logic sim, more test fixtures
7 months ago
f6baf9cb5e
a fast 6v sim
7 months ago
Stefan Holst
1a3b91c1c0
fix comment
11 months ago
aa7536b8b0
line use and diff
11 months ago
a6d1e4099c
alap toposort, improve tests
1 year ago
4bb3f3424a
cond in sdf parser. ignored for now.
1 year ago
baeb759824
types, perf op growing list, keep s_nodes
1 year ago
967a232b1c
fix pulse threshold selection
1 year ago
351d809306
for release 0.0.4
...
- Circuit: is now pickleable and comparable
- Circuit: utilities for locating/indexing io-ports
- Verilog: parser fixes, support yosys-style verilog
- SDF: parser fixes, full XOR support
- STIL: parser fixes
- Simulators: faster, up to 4-input cells, pickleable
- WaveSim: WSA calculation support
- WaveSim: Per-simulation parameters and delays
- Logic: Data are now raw numpy arrays
- Logic: More tools for bit-packing
- Added DEF parser
- Better techlib support for NanGate, SAED, GSC180
- Tests and docs improvements
1 year ago
0ade89defa
remove old test data, intro check
1 year ago
35e727e714
better docs, new techlib as default, fix tests
1 year ago
280c425486
fix test
1 year ago
cf9a98b5ce
del deprecated sdf code, explicit tlib use
1 year ago
5a693f7b9b
preserve node order during resolve
1 year ago
ea45a326ec
add latch, fix xor delays, improve test
1 year ago
d97555e9e9
fix simprim cells, add saed90
1 year ago
afb0a64953
wsa accumulation in wavesim
1 year ago
670fb0b3fc
circuit node substitution
1 year ago
f8bf579be2
support concat, bus select, ISOL cells
1 year ago
f61e2b42e8
support more cells in logic sim
1 year ago
0b15f9fa18
doc improvements
1 year ago
dc76a9f517
new into demo
1 year ago
7a060b1831
support for static variations
2 years ago
44b0c887d7
random sampling of delays
2 years ago
5566b80e52
simprim, vat refactor, batchrange
2 years ago
1eb8d87884
faster logic sim, removing MVArray, BPArray
2 years ago
8da4a62bce
switch to new wave_sim, silence occupancy warnings
2 years ago
Stefan Holst
3497bfdc75
first gpu-code, cached test fixtures
2 years ago
Stefan Holst
f1ebe1487c
new wave sim
2 years ago
Stefan Holst
f0dac36ac7
interface -> io_nodes, io_loc fix
2 years ago
840b816804
Circuit pickle, STIL/SDF/techlib fixes, sdata
...
- fix pin indices for various SC lib variants
- SDF annotation improvements
- STIL loading improvements
- Support for per-simulation parameters in WaveSim
- Circuit is now pickleable and comparable
2 years ago
d59d6401c8
fix stil loading and logic sim capture
3 years ago
387c436207
fix tests, version bump
3 years ago
0251d66d28
make circuit pickable and comparable
4 years ago
864230b883
initial letch support, fix capture in logic sim
4 years ago
c9445f2d79
Docs, __index__, fault injection and TechLib
...
- Documentation improvements
- Node and Line objects now provide __index__
- LogicSim cleanup and improvements (inject_cb, cycle, ...)
- Introduce TechLib class to organize tech-specific info
- More human-readable output
- De-linting
4 years ago
62cf56e98a
TechLib class, remove unnecessary .index
4 years ago
ff4de6d782
de-lint and repr improvements
4 years ago
64e1de396f
New m-valued logic arrays, documentation, 0.0.2
...
- MVArray for multi-valued logic
- BPArray for bit-parallel storage layout
- Started documenting with Sphinx
- Migrated simulators to new BPArray
4 years ago
7f035c1ac5
Migration to new logic value representation
4 years ago
7bcfbf502b
Documentation, cleanup, multi-valued logic
4 years ago
5830608527
Documenting circuit module
4 years ago
a77ac4a397
start designing new data structures for m-valued logic
4 years ago
e6ae009969
updated b14 benchmark, update wavesim capture api, expand usage examples
4 years ago
6bba7ac359
support for stripping forks and memory re-use in wavesim.
4 years ago
1af346c97a
overflow notification and wavecap statistics on GPU
4 years ago
0c5a7f56e1
Project Import
4 years ago
Stefan Holst
Stefan Holst
stefan