Stefan Holst
93a0858d2f
oai and aoi pin handling fix
2023-01-16 17:37:41 +09:00
Stefan Holst
1f2808ee31
Merge branch 'main' into devel
2022-07-21 22:10:20 +09:00
Stefan Holst
840b816804
Circuit pickle, STIL/SDF/techlib fixes, sdata
...
- fix pin indices for various SC lib variants
- SDF annotation improvements
- STIL loading improvements
- Support for per-simulation parameters in WaveSim
- Circuit is now pickleable and comparable
2022-07-21 22:01:51 +09:00
Stefan Holst
163b348a0c
year bump
2022-07-21 18:47:25 +09:00
Stefan Holst
ecfc692edc
support reset RN for scan cells
2022-07-21 17:16:59 +09:00
Stefan Holst
afb7e745a1
adding aoi to logic sim
2022-07-21 17:16:59 +09:00
Stefan Holst
c530983afa
accept I as a first input
2022-03-17 14:57:37 +09:00
Stefan Holst
775b13c694
fix off-by-1 pin index when loading AOI and OAI cells
2022-02-02 15:05:14 +09:00
Stefan Holst
584445f3b1
wave eval for 4-input gates
2021-11-22 14:54:38 +09:00
Stefan Holst
85dd02d4d7
interpret N as unassigned in STIL
2021-11-07 18:51:41 +09:00
Stefan Holst
7c03271048
improve robustness of sdf annotation and wave sim
2021-09-01 12:57:55 +09:00
Stefan Holst
8bbaaf8fae
comment change
2021-07-26 10:52:33 +09:00
Stefan Holst
d59d6401c8
fix stil loading and logic sim capture
2021-07-22 17:21:58 +09:00
Stefan Holst
387c436207
fix tests, version bump
2021-07-19 14:14:35 +09:00
Stefan Holst
b981b1153c
add sdata to control individual sims
2021-06-17 12:05:55 +09:00
Stefan Holst
c3e4090f31
make nodes and lines hashable again
2021-03-28 19:44:19 +09:00
Stefan Holst
0251d66d28
make circuit pickable and comparable
2021-03-28 19:35:19 +09:00
Stefan Holst
864230b883
initial letch support, fix capture in logic sim
2021-03-25 10:36:55 +09:00
Stefan Holst
8434f5e694
fixes for IWLS benchmark netlists
2021-01-31 16:40:00 +09:00
Stefan Holst
82a53e0171
improve techlib for gsclib, better constant handling in verilog parser
2021-01-31 13:41:36 +09:00
Stefan Holst
a2df0e5682
fix ff annotation
2021-01-22 18:03:18 +09:00
Stefan Holst
9c8dee31b9
assign and capture return arrays, new cycle method for common use pattern
2021-01-14 20:47:22 +09:00
Stefan Holst
2bbdf3ee5d
fix logic sim of DFF.QN output
2021-01-14 15:05:39 +09:00
Stefan Holst
c12a30328c
better hr_time
2021-01-12 15:18:37 +09:00
Stefan Holst
4f531fe4cb
implement logging range
2021-01-06 12:54:14 +09:00
Stefan Holst
5084f1dd8c
demo nb run with cuda
2020-12-21 20:13:48 +09:00
Stefan Holst
765cb70ca3
add logic depth example
2020-12-03 12:15:35 +09:00
Stefan Holst
e6ae009969
updated b14 benchmark, update wavesim capture api, expand usage examples
2020-11-29 22:32:47 +09:00
Stefan Holst
e1101b5b70
fix loading of stuck-at fault patterns, support ibuff cell
2020-11-29 14:50:16 +09:00
Stefan Holst