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Commit Graph

8 Commits (5769aa3716f85f547cf4f2e07ffc5f0e80c8daac)

Author	SHA1	Message	Date
Stefan Holst	baeb759824	types, perf op growing list, keep s_nodes	2 years ago
Stefan Holst	351d809306	for release 0.0.4 ... - Circuit: is now pickleable and comparable - Circuit: utilities for locating/indexing io-ports - Verilog: parser fixes, support yosys-style verilog - SDF: parser fixes, full XOR support - STIL: parser fixes - Simulators: faster, up to 4-input cells, pickleable - WaveSim: WSA calculation support - WaveSim: Per-simulation parameters and delays - Logic: Data are now raw numpy arrays - Logic: More tools for bit-packing - Added DEF parser - Better techlib support for NanGate, SAED, GSC180 - Tests and docs improvements	2 years ago
Stefan Holst	280c425486	fix test	2 years ago
Stefan Holst	5a693f7b9b	preserve node order during resolve	2 years ago
Stefan Holst	670fb0b3fc	circuit node substitution	2 years ago
Stefan Holst	f0dac36ac7	interface -> io_nodes, io_loc fix	2 years ago
Stefan Holst	840b816804	Circuit pickle, STIL/SDF/techlib fixes, sdata ... - fix pin indices for various SC lib variants - SDF annotation improvements - STIL loading improvements - Support for per-simulation parameters in WaveSim - Circuit is now pickleable and comparable	3 years ago
Stefan Holst	0251d66d28	make circuit pickable and comparable	4 years ago
Stefan Holst	64e1de396f	New m-valued logic arrays, documentation, 0.0.2 ... - MVArray for multi-valued logic - BPArray for bit-parallel storage layout - Started documenting with Sphinx - Migrated simulators to new BPArray	4 years ago
Stefan Holst	5830608527	Documenting circuit module	4 years ago
Stefan Holst	0c5a7f56e1	Project Import	5 years ago