kyupy

Commit Graph

Author	SHA1	Message	Date
Stefan Holst	aea633ac8d	for release 0.0.5 * Techlib: fix NanGate variants * Circuit: more visitor and manipulator utilities * mv_transition: produce stable values when arguments are UNASSIGNED * Verilog: better assign processing * STIL parsing improvements * SDF: conditional parsing (semantics ignored for now), better interconnect annotation, more robust name matching * sim: use ALAP topo-sort * logic_sim: improved fault injection, faster 6V sim * wave_sim: use correct thresholds for pulse filtering, partial delta-sim support, per-sim delay factor * log: fix limiter	4 months ago
Stefan Holst	a4b7364478	mux21 in 6v logic sim, more test fixtures	2 years ago
Stefan Holst	f6baf9cb5e	a fast 6v sim	2 years ago
Stefan Holst	a6d1e4099c	alap toposort, improve tests	2 years ago
Stefan Holst	351d809306	for release 0.0.4 - Circuit: is now pickleable and comparable - Circuit: utilities for locating/indexing io-ports - Verilog: parser fixes, support yosys-style verilog - SDF: parser fixes, full XOR support - STIL: parser fixes - Simulators: faster, up to 4-input cells, pickleable - WaveSim: WSA calculation support - WaveSim: Per-simulation parameters and delays - Logic: Data are now raw numpy arrays - Logic: More tools for bit-packing - Added DEF parser - Better techlib support for NanGate, SAED, GSC180 - Tests and docs improvements	2 years ago
Stefan Holst	d97555e9e9	fix simprim cells, add saed90	2 years ago
stefan	1eb8d87884	faster logic sim, removing MVArray, BPArray	3 years ago
Stefan Holst	840b816804	Circuit pickle, STIL/SDF/techlib fixes, sdata - fix pin indices for various SC lib variants - SDF annotation improvements - STIL loading improvements - Support for per-simulation parameters in WaveSim - Circuit is now pickleable and comparable	3 years ago
Stefan Holst	d59d6401c8	fix stil loading and logic sim capture	4 years ago
Stefan Holst	864230b883	initial letch support, fix capture in logic sim	5 years ago
Stefan Holst	c9445f2d79	Docs, __index__, fault injection and TechLib - Documentation improvements - Node and Line objects now provide __index__ - LogicSim cleanup and improvements (inject_cb, cycle, ...) - Introduce TechLib class to organize tech-specific info - More human-readable output - De-linting	5 years ago
Stefan Holst	ff4de6d782	de-lint and repr improvements	5 years ago
Stefan Holst	64e1de396f	New m-valued logic arrays, documentation, 0.0.2 - MVArray for multi-valued logic - BPArray for bit-parallel storage layout - Started documenting with Sphinx - Migrated simulators to new BPArray	5 years ago
Stefan Holst	7f035c1ac5	Migration to new logic value representation	5 years ago
Stefan Holst	7bcfbf502b	Documentation, cleanup, multi-valued logic	5 years ago
Stefan Holst	0c5a7f56e1	Project Import	5 years ago

11 Commits (469dc18aa9fd259fa9f264de5eabb15181e0a1b6)