stefan
1f984c9bd9
faster fanout generator function
2026-05-15 17:19:34 +09:00
stefan
0c8a2b7746
add return type
2026-05-14 08:20:07 +09:00
stefan
f66953f2d3
fix sim model gen for undriven outputs
2026-05-11 23:46:18 +09:00
stefan
7203145a1d
better docs and repr
2026-05-11 23:33:41 +09:00
stefan
32e0766d41
s_len param for vcd
2026-05-11 23:33:07 +09:00
stefan
9570161744
fix half adder
2026-05-11 23:32:25 +09:00
stefan
a594e2fb9a
annotation and repr
2026-05-10 23:57:52 +09:00
stefan
1bc9dc0e9d
bench parsing docs
2026-05-09 14:41:57 +09:00
stefan
c5bdeb4a68
add type annotation
2026-05-08 18:48:15 +09:00
stefan
67db64611b
fix cuda launch expecting pure ints for grid spec
2026-05-08 18:47:59 +09:00
stefan
7a9ed1e536
vcd improvements
2026-05-07 20:50:08 +09:00
stefan
fcd9b78c24
rm test.py
2026-05-06 23:39:49 +09:00
stefan
f975765bbb
first version of a vcd parser
2026-05-06 23:38:30 +09:00
stefan
3cb1b2bc86
first version of a vcd parser
2026-05-06 23:34:48 +09:00
stefan
c4aecbd6c9
skywater 130nm tech library
2026-04-26 22:17:03 +09:00
stefan
25ff1fb2dc
fixups for empty standard cells
2026-04-26 22:16:32 +09:00
stefan
f0b55eed27
version bump
2025-11-27 22:01:32 +09:00
stefan
3700ae9b33
need 3.12 for generic types
2025-11-27 21:59:06 +09:00
stefan
df695e0aa1
for release 0.0.6
...
- sim: added LogicSim2V, LogicSim4V, LogicSim6V (faster and simpler API)
- sim: fixed model for: many-input gates in bench; dangling nodes; POs that drive further logic
- Circuit: dot output fix and better style, fixed equivalence check of lines and nodes.
- Techlib: Added KYUPY library with supported simulation primitives for debug and testing
- tests: fixed and added more for better coverage
- more type annotations
- updated project config and dependencies for better uv experience, newer lark, newer numpy
2025-11-27 21:59:06 +09:00
stefan
a28128830d
beginning simple always block parsing in verilog
2025-11-27 21:19:59 +09:00
stefan
20cf441abb
add doc gen dependencies
2025-11-23 22:48:16 +09:00
stefan
5ac21edbb1
migrate readme to markdown
2025-11-23 22:39:31 +09:00
stefan
f0d74777af
add dff to techlib
2025-11-23 21:35:49 +09:00
stefan
3848665533
ignore more generated python files
2025-11-23 21:35:30 +09:00
stefan
541cccd756
fix sim model for PO that also drive further logic
2025-11-23 21:34:58 +09:00
stefan
fed66f85cb
fix oob in test
2025-11-23 21:31:56 +09:00
stefan
2eb10f83b0
add pytest dev dependency
2025-11-23 21:31:40 +09:00
stefan
dd4e5c861a
fix sim model generation for circuits with dangling nodes
2025-11-20 15:28:41 +09:00
stefan
9cebbcce8f
support for storing responses separately
2025-11-11 18:13:08 +09:00
stefan
31434cfd51
4v sim, fixed 6v sim, better testing
2025-11-09 08:09:46 +09:00
stefan
ce94210b52
adding more types
2025-11-09 08:08:03 +09:00
stefan
09420fd72c
new logic sim interface prototype, simprim lib and test
2025-11-02 20:56:14 +09:00
stefan
5bcc1c1d77
new synthetic techlib with kyupy simprims
2025-11-02 20:49:37 +09:00
stefan
df8a58f57b
generate proper simprims in bench parser
2025-11-02 20:44:04 +09:00
stefan
3dfd0cb60d
euivalence test, op format doc
2025-10-31 17:13:58 +09:00
stefan
21439e3595
circuit objects and nodes/lines of different circuits are not quivalent.
2025-10-31 17:12:50 +09:00
stefan
88a5c79161
dot fix and updated intro nb
2025-10-23 22:48:18 +09:00
stefan
9ca437fe47
fault injection for 4v sim, wave_sim test fix
2025-10-23 21:26:52 +09:00
stefan
0cdaf71963
fix for latest lark
2025-10-23 21:25:50 +09:00
stefan
75972d7bb2
numba config deprecated
2025-10-23 21:25:36 +09:00
stefan
469dc18aa9
lark dependency update
2025-10-23 18:20:29 +09:00
stefan
33addab141
fix output with newest numpy
2025-10-22 14:17:44 +09:00
stefan
674f3dea4a
Merge branch 'main' into devel
2025-06-23 16:06:02 +09:00
stefan
55d62ff354
sphinx config
2025-06-23 15:54:31 +09:00
stefan
e311b1098a
sphinx config
2025-06-23 15:45:35 +09:00
stefan
aea633ac8d
for release 0.0.5
...
* Techlib: fix NanGate variants
* Circuit: more visitor and manipulator utilities
* mv_transition: produce stable values when arguments are UNASSIGNED
* Verilog: better assign processing
* STIL parsing improvements
* SDF: conditional parsing (semantics ignored for now), better interconnect annotation, more robust name matching
* sim: use ALAP topo-sort
* logic_sim: improved fault injection, faster 6V sim
* wave_sim: use correct thresholds for pulse filtering, partial delta-sim support, per-sim delay factor
* log: fix limiter
2025-06-23 15:39:55 +09:00
stefan
187d176cfd
partial ternary if support
2025-06-02 12:20:42 +09:00
stefan
ba1de0bea9
support for per-simulation delay factors
2025-01-17 13:17:44 +09:00
stefan
5769aa3716
deactivate delta sim
2025-01-17 11:28:12 +09:00
stefan
e97c370d39
support stuck-at fault model injection for 2-valued logic sim
2024-12-06 13:42:22 +09:00
stefan
stefan