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Commit Graph

117 Commits (1e9fe7707be1097dc39bca0eb7c99e5f0cc31b1b)

 

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Author	SHA1	Message	Date
Stefan Holst	3774b14286	support ppi/ppo	2 years ago
Stefan Holst	4847ad9c40	locating io ports and busses by name	2 years ago
Stefan Holst	6801606dca	new common scheduler for simulators	2 years ago
Stefan Holst	faf41f0863	ff transitions switch	2 years ago
Stefan Holst	6430f10f73	HADD pin index fix	2 years ago
Stefan Holst	fa19af8c31	4-input gate simulator	2 years ago
Stefan Holst	93a0858d2f	oai and aoi pin handling fix	2 years ago
Stefan Holst	1f2808ee31	Merge branch 'main' into devel	2 years ago
Stefan Holst	840b816804	Circuit pickle, STIL/SDF/techlib fixes, sdata ... - fix pin indices for various SC lib variants - SDF annotation improvements - STIL loading improvements - Support for per-simulation parameters in WaveSim - Circuit is now pickleable and comparable	2 years ago
Stefan Holst	163b348a0c	year bump	2 years ago
Stefan Holst	ecfc692edc	support reset RN for scan cells	2 years ago
Stefan Holst	afb7e745a1	adding aoi to logic sim	2 years ago
Stefan Holst	6a8841c3c6	revert wave_eval4	2 years ago
Stefan Holst	c530983afa	accept I as a first input	3 years ago
Stefan Holst	775b13c694	fix off-by-1 pin index when loading AOI and OAI cells	3 years ago
Stefan Holst	584445f3b1	wave eval for 4-input gates	3 years ago
Stefan Holst	85dd02d4d7	interpret N as unassigned in STIL	3 years ago
Stefan Holst	7c03271048	improve robustness of sdf annotation and wave sim	3 years ago
Stefan Holst	8bbaaf8fae	comment change	3 years ago
Stefan Holst	d59d6401c8	fix stil loading and logic sim capture	3 years ago
Stefan Holst	387c436207	fix tests, version bump	3 years ago
Stefan Holst	b981b1153c	add sdata to control individual sims	4 years ago
Stefan Holst	87d93afb44	fix time in unpickled log objects	4 years ago
Stefan Holst	c3e4090f31	make nodes and lines hashable again	4 years ago
Stefan Holst	0251d66d28	make circuit pickable and comparable	4 years ago
Stefan Holst	864230b883	initial letch support, fix capture in logic sim	4 years ago
Stefan Holst	d05841a6a2	Merge branch 'main' into devel	4 years ago
Stefan Holst	b17ab2d148	fixes for IWLS benchmark netlists and older STIL files	4 years ago
Stefan Holst	c5be32d7e5	doc and indent fix	4 years ago
Stefan Holst	8434f5e694	fixes for IWLS benchmark netlists	4 years ago
Stefan Holst	9ff2369a55	fix parsing older stil files	4 years ago
Stefan Holst	82a53e0171	improve techlib for gsclib, better constant handling in verilog parser	4 years ago
Stefan Holst	a2df0e5682	fix ff annotation	4 years ago
Stefan Holst	ec37e11fef	Merge branch 'main' into devel	4 years ago
Stefan Holst	c9445f2d79	Docs, __index__, fault injection and TechLib ... - Documentation improvements - Node and Line objects now provide __index__ - LogicSim cleanup and improvements (inject_cb, cycle, ...) - Introduce TechLib class to organize tech-specific info - More human-readable output - De-linting	4 years ago
Stefan Holst	3a5a3c128b	year bump	4 years ago
Stefan Holst	ee30898cef	docs for numba and cuda	4 years ago
Stefan Holst	62cf56e98a	TechLib class, remove unnecessary .index	4 years ago
Stefan Holst	dc003fa624	documentation improvements	4 years ago
Stefan Holst	8b5a71f498	documentation improvements	4 years ago
Stefan Holst	9c8dee31b9	assign and capture return arrays, new cycle method for common use pattern	4 years ago
Stefan Holst	2bbdf3ee5d	fix logic sim of DFF.QN output	4 years ago
Stefan Holst	35cf63cf38	Make Node and Line indexable, documentation.	4 years ago
Stefan Holst	ff4de6d782	de-lint and repr improvements	4 years ago
Stefan Holst	c12a30328c	better hr_time	4 years ago
Stefan Holst	7e6660002b	support ibuff in WaveSim	4 years ago
Stefan Holst	dfbc35eeb9	logging range fixes	4 years ago
Stefan Holst	4f531fe4cb	implement logging range	4 years ago
Stefan Holst	18c17b5f76	more docs and reprs	4 years ago
Stefan Holst	0bad95e94e	LogicSim clean-up and new fault injection facility. version bump.	4 years ago