8 Commits
Author SHA1 Message Date
Stefan Holst 9f9902c613 remove _static 2023-07-22 16:48:51 +09:00
Stefan Holst eb4e0f4529 improve readthedocs config 2023-07-22 16:40:57 +09:00
Stefan Holst 821ead0c7a add readthedocs conf for py3.8 2023-07-22 16:34:57 +09:00
Stefan Holst 351d809306 for release 0.0.4
- Circuit: is now pickleable and comparable
- Circuit: utilities for locating/indexing io-ports
- Verilog: parser fixes, support yosys-style verilog
- SDF: parser fixes, full XOR support
- STIL: parser fixes
- Simulators: faster, up to 4-input cells, pickleable
- WaveSim: WSA calculation support
- WaveSim: Per-simulation parameters and delays
- Logic: Data are now raw numpy arrays
- Logic: More tools for bit-packing
- Added DEF parser
- Better techlib support for NanGate, SAED, GSC180
- Tests and docs improvements
2023-07-22 16:13:01 +09:00
Stefan Holst 840b816804 Circuit pickle, STIL/SDF/techlib fixes, sdata
- fix pin indices for various SC lib variants
- SDF annotation improvements
- STIL loading improvements
- Support for per-simulation parameters in WaveSim
- Circuit is now pickleable and comparable
2022-07-21 22:01:51 +09:00
Stefan Holst 765cb70ca3 add logic depth example 2020-12-03 12:15:35 +09:00
Stefan Holst e6ae009969 updated b14 benchmark, update wavesim capture api, expand usage examples 2020-11-29 22:32:47 +09:00
Stefan Holst e1101b5b70 fix loading of stuck-at fault patterns, support ibuff cell 2020-11-29 14:50:16 +09:00