Browse Source

fix tests, version bump

devel
Stefan Holst 3 years ago
parent
commit
387c436207
  1. 2
      setup.py
  2. 3
      src/kyupy/logic_sim.py
  3. 4
      src/kyupy/stil.py
  4. 15
      tests/test_stil.py
  5. 20
      tests/test_wave_sim.py

2
setup.py

@ -5,7 +5,7 @@ with open('README.rst', 'r') as f:
setup( setup(
name='kyupy', name='kyupy',
version='0.0.3', version='0.0.4',
description='High-performance processing and analysis of non-hierarchical VLSI designs', description='High-performance processing and analysis of non-hierarchical VLSI designs',
long_description=long_description, long_description=long_description,
long_description_content_type='text/x-rst', long_description_content_type='text/x-rst',

3
src/kyupy/logic_sim.py

@ -111,7 +111,8 @@ class LogicSim:
resp[1, :] = ~self.state[node.outs[1], 0, :] # assume QN is connected, take inverse of that. resp[1, :] = ~self.state[node.outs[1], 0, :] # assume QN is connected, take inverse of that.
else: else:
resp[1, :] = self.state[node.outs[0], 0, :] resp[1, :] = self.state[node.outs[0], 0, :]
resp[..., 2, :] = resp[..., 0, :] ^ resp[..., 1, :] if self.m > 4:
resp[..., 2, :] = resp[..., 0, :] ^ resp[..., 1, :]
# We don't handle X or - correctly. # We don't handle X or - correctly.
return responses return responses

4
src/kyupy/stil.py

@ -41,7 +41,7 @@ class StilFile:
for so_port in self.so_ports: for so_port in self.so_ports:
if so_port in call.parameters: if so_port in call.parameters:
unload[so_port] = call.parameters[so_port].replace('\n', '') unload[so_port] = call.parameters[so_port].replace('\n', '')
if len(launch) > 0: if len(capture) > 0:
self.patterns.append(ScanPattern(sload, launch, capture, unload)) self.patterns.append(ScanPattern(sload, launch, capture, unload))
capture = {} capture = {}
launch = {} launch = {}
@ -96,7 +96,7 @@ class StilFile:
for si_port in self.si_ports.keys(): for si_port in self.si_ports.keys():
pattern = logic.mv_xor(p.load[si_port], scan_inversions[si_port]) pattern = logic.mv_xor(p.load[si_port], scan_inversions[si_port])
tests.data[scan_maps[si_port], i] = pattern.data[:, 0] tests.data[scan_maps[si_port], i] = pattern.data[:, 0]
tests.data[pi_map, i] = logic.MVArray(p.launch['_pi']).data[:, 0] tests.data[pi_map, i] = logic.MVArray(p.capture['_pi']).data[:, 0]
return tests return tests
def tests_loc(self, circuit): def tests_loc(self, circuit):

15
tests/test_stil.py

@ -1,8 +1,21 @@
from kyupy import stil from kyupy import stil, verilog
def test_b14(mydir): def test_b14(mydir):
b14 = verilog.load(mydir / 'b14.v.gz')
s = stil.load(mydir / 'b14.stuck.stil.gz') s = stil.load(mydir / 'b14.stuck.stil.gz')
assert len(s.signal_groups) == 10 assert len(s.signal_groups) == 10
assert len(s.scan_chains) == 1 assert len(s.scan_chains) == 1
assert len(s.calls) == 2163 assert len(s.calls) == 2163
tests = s.tests(b14)
resp = s.responses(b14)
assert len(tests) > 0
assert len(resp) > 0
#s2 = stil.load(mydir / 'b14.transition.stil.gz')
#tests = s2.tests_loc(b14)
#resp = s2.responses(b14)
#assert len(tests) > 0
#assert len(resp) > 0

20
tests/test_wave_sim.py

@ -29,20 +29,22 @@ def test_wave_eval():
sat[1] = 16, 16, 0 sat[1] = 16, 16, 0
sat[2] = 32, 16, 0 sat[2] = 32, 16, 0
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times) sdata = np.asarray([1, -1, 0, 0], dtype='float32')
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
assert z[0] == TMIN assert z[0] == TMIN
a[0] = TMIN a[0] = TMIN
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times) wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
assert z[0] == TMIN assert z[0] == TMIN
b[0] = TMIN b[0] = TMIN
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times) wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
assert z[0] == TMAX assert z[0] == TMAX
a[0] = 1 # A _/^^^ a[0] = 1 # A _/^^^
b[0] = 2 # B __/^^ b[0] = 2 # B __/^^
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times) wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
assert z[0] == TMIN # ^^^\___ B -> Z fall delay assert z[0] == TMIN # ^^^\___ B -> Z fall delay
assert z[1] == 2.4 assert z[1] == 2.4
assert z[2] == TMAX assert z[2] == TMAX
@ -50,7 +52,7 @@ def test_wave_eval():
a[0] = TMIN # A ^^^^^^ a[0] = TMIN # A ^^^^^^
b[0] = TMIN # B ^^^\__ b[0] = TMIN # B ^^^\__
b[1] = 2 b[1] = 2
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times) wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
assert z[0] == 2.3 # ___/^^^ B -> Z rise delay assert z[0] == 2.3 # ___/^^^ B -> Z rise delay
assert z[1] == TMAX assert z[1] == TMAX
@ -59,7 +61,7 @@ def test_wave_eval():
b[0] = TMIN b[0] = TMIN
b[1] = 2 # B ^^\__/^^ b[1] = 2 # B ^^\__/^^
b[2] = 2.35 b[2] = 2.35
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times) wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
assert z[0] == 2.3 # __/^^\__ assert z[0] == 2.3 # __/^^\__
assert z[1] == 2.75 assert z[1] == 2.75
assert z[2] == TMAX assert z[2] == TMAX
@ -69,7 +71,7 @@ def test_wave_eval():
b[0] = 2 # B __/^^\__ b[0] = 2 # B __/^^\__
b[1] = 2.45 b[1] = 2.45
b[2] = TMAX b[2] = TMAX
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times) wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
assert z[0] == TMIN # ^^\__/^^ assert z[0] == TMIN # ^^\__/^^
assert z[1] == 2.4 assert z[1] == 2.4
assert z[2] == 2.75 assert z[2] == 2.75
@ -80,7 +82,7 @@ def test_wave_eval():
b[0] = 2 # B __/^^\__ b[0] = 2 # B __/^^\__
b[1] = 2.35 b[1] = 2.35
b[2] = TMAX b[2] = TMAX
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times) wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
assert z[0] == TMIN # ^^^^^^ assert z[0] == TMIN # ^^^^^^
assert z[1] == TMAX assert z[1] == TMAX
@ -89,7 +91,7 @@ def test_wave_eval():
b[0] = TMIN b[0] = TMIN
b[1] = 2 # B ^^\__/^^ b[1] = 2 # B ^^\__/^^
b[2] = 2.25 b[2] = 2.25
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times) wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
assert z[0] == TMAX # ______ assert z[0] == TMAX # ______

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