diff --git a/setup.py b/setup.py
index efb49ec..0f443ff 100644
--- a/setup.py
+++ b/setup.py
@@ -5,7 +5,7 @@ with open('README.rst', 'r') as f:
 
 setup(
     name='kyupy',
-    version='0.0.3',
+    version='0.0.4',
     description='High-performance processing and analysis of non-hierarchical VLSI designs',
     long_description=long_description,
     long_description_content_type='text/x-rst',
diff --git a/src/kyupy/logic_sim.py b/src/kyupy/logic_sim.py
index fd227fc..13156aa 100644
--- a/src/kyupy/logic_sim.py
+++ b/src/kyupy/logic_sim.py
@@ -111,7 +111,8 @@ class LogicSim:
                     resp[1, :] = ~self.state[node.outs[1], 0, :]  # assume QN is connected, take inverse of that.
                 else:
                     resp[1, :] = self.state[node.outs[0], 0, :]
-                resp[..., 2, :] = resp[..., 0, :] ^ resp[..., 1, :]
+                if self.m > 4:
+                    resp[..., 2, :] = resp[..., 0, :] ^ resp[..., 1, :]
                 # We don't handle X or - correctly.
 
         return responses
diff --git a/src/kyupy/stil.py b/src/kyupy/stil.py
index c0c789d..7a20a5b 100644
--- a/src/kyupy/stil.py
+++ b/src/kyupy/stil.py
@@ -41,7 +41,7 @@ class StilFile:
                 for so_port in self.so_ports:
                     if so_port in call.parameters:
                         unload[so_port] = call.parameters[so_port].replace('\n', '')
-                if len(launch) > 0:
+                if len(capture) > 0:
                     self.patterns.append(ScanPattern(sload, launch, capture, unload))
                     capture = {}
                     launch = {}
@@ -96,7 +96,7 @@ class StilFile:
             for si_port in self.si_ports.keys():
                 pattern = logic.mv_xor(p.load[si_port], scan_inversions[si_port])
                 tests.data[scan_maps[si_port], i] = pattern.data[:, 0]
-            tests.data[pi_map, i] = logic.MVArray(p.launch['_pi']).data[:, 0]
+            tests.data[pi_map, i] = logic.MVArray(p.capture['_pi']).data[:, 0]
         return tests
 
     def tests_loc(self, circuit):
diff --git a/tests/test_stil.py b/tests/test_stil.py
index 63f19e4..77dbbb1 100644
--- a/tests/test_stil.py
+++ b/tests/test_stil.py
@@ -1,8 +1,21 @@
-from kyupy import stil
+from kyupy import stil, verilog
 
 
 def test_b14(mydir):
+    b14 = verilog.load(mydir / 'b14.v.gz')
+    
     s = stil.load(mydir / 'b14.stuck.stil.gz')
     assert len(s.signal_groups) == 10
     assert len(s.scan_chains) == 1
     assert len(s.calls) == 2163
+    tests = s.tests(b14)
+    resp = s.responses(b14)
+    assert len(tests) > 0
+    assert len(resp) > 0
+    
+    #s2 = stil.load(mydir / 'b14.transition.stil.gz')
+    #tests = s2.tests_loc(b14)
+    #resp = s2.responses(b14)
+    #assert len(tests) > 0
+    #assert len(resp) > 0
+
diff --git a/tests/test_wave_sim.py b/tests/test_wave_sim.py
index 8ddb94d..724a415 100644
--- a/tests/test_wave_sim.py
+++ b/tests/test_wave_sim.py
@@ -29,20 +29,22 @@ def test_wave_eval():
     sat[1] = 16, 16, 0
     sat[2] = 32, 16, 0
 
-    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
+    sdata = np.asarray([1, -1, 0, 0], dtype='float32')
+
+    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
     assert z[0] == TMIN
 
     a[0] = TMIN
-    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
+    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
     assert z[0] == TMIN
 
     b[0] = TMIN
-    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
+    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
     assert z[0] == TMAX
 
     a[0] = 1  # A _/^^^
     b[0] = 2  # B __/^^
-    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
+    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
     assert z[0] == TMIN  # ^^^\___ B -> Z fall delay
     assert z[1] == 2.4
     assert z[2] == TMAX
@@ -50,7 +52,7 @@ def test_wave_eval():
     a[0] = TMIN  # A ^^^^^^
     b[0] = TMIN  # B ^^^\__
     b[1] = 2
-    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
+    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
     assert z[0] == 2.3  # ___/^^^ B -> Z rise delay
     assert z[1] == TMAX
 
@@ -59,7 +61,7 @@ def test_wave_eval():
     b[0] = TMIN
     b[1] = 2     # B ^^\__/^^
     b[2] = 2.35
-    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
+    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
     assert z[0] == 2.3  # __/^^\__
     assert z[1] == 2.75
     assert z[2] == TMAX
@@ -69,7 +71,7 @@ def test_wave_eval():
     b[0] = 2  # B __/^^\__
     b[1] = 2.45
     b[2] = TMAX
-    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
+    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
     assert z[0] == TMIN  # ^^\__/^^
     assert z[1] == 2.4
     assert z[2] == 2.75
@@ -80,7 +82,7 @@ def test_wave_eval():
     b[0] = 2  # B __/^^\__
     b[1] = 2.35
     b[2] = TMAX
-    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
+    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
     assert z[0] == TMIN  # ^^^^^^
     assert z[1] == TMAX
 
@@ -89,7 +91,7 @@ def test_wave_eval():
     b[0] = TMIN
     b[1] = 2  # B ^^\__/^^
     b[2] = 2.25
-    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
+    wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
     assert z[0] == TMAX  # ______