stefan/kyupy
2
0 Fork 0
Code Issues Pull Requests Releases Wiki Activity

one-bit busses

Browse Source
This commit is contained in:
Stefan Holst committed 2023-07-12 16:32:08 +09:00
1 parent b098fb219d
commit 08d9f5a9bf
1 file changed
+15 -5
Download Patch File Download Diff File Expand all files Collapse all files
src/kyupy/verilog.py
+15 -5
View File
@@ -126,6 +126,10 @@ class VerilogTransformer(Transformer):
n = Node(c, stmt.name, kind=stmt.type)
for p, s in stmt.pins.items():
if self.tlib.pin_is_output(n.kind, p):
if s in sig_decls:
s = sig_decls[s].names
if isinstance(s, list) and len(s) == 1:
s = s[0]
Line(c, (n, self.tlib.pin_index(stmt.type, p)), Node(c, s))
elif hasattr(stmt, 'data') and stmt.data == 'assign':
assignments.append((stmt.children[0], stmt.children[1]))
@@ -175,8 +179,11 @@ class VerilogTransformer(Transformer):
s = cname
Line(c, cnode, Node(c, s))
if s not in c.forks:
log.warn(f'Signal not driven: {s}')
Node(c, s) # generate fork here
if f'{s}[0]' in c.forks: # actually a 1-bit bus?
s = f'{s}[0]'
else:
log.warn(f'Signal not driven: {s}')
Node(c, s) # generate fork here
fork = c.forks[s]
if self.branchforks:
branchfork = Node(c, fork.name + "~" + n.name + "/" + p)
@@ -187,9 +194,12 @@ class VerilogTransformer(Transformer):
if sd.kind == 'output':
for name in sd.names:
if name not in c.forks:
log.warn(f'Output not driven: {name}')
else:
Line(c, c.forks[name], c.cells[name])
if f'{name}[0]' in c.forks: # actually a 1-bit bus?
name = f'{name}[0]'
else:
log.warn(f'Output not driven: {name}')
continue
Line(c, c.forks[name], c.cells[name])
return c
@staticmethod