one-bit busses

src/kyupy/verilog.py

@@ -126,6 +126,10 @@ class VerilogTransformer(Transformer):
                 n = Node(c, stmt.name, kind=stmt.type)
                 for p, s in stmt.pins.items():
                     if self.tlib.pin_is_output(n.kind, p):
+                        if s in sig_decls:
+                            s = sig_decls[s].names
+                            if isinstance(s, list) and len(s) == 1:
+                                s = s[0]
                         Line(c, (n, self.tlib.pin_index(stmt.type, p)), Node(c, s))
             elif hasattr(stmt, 'data') and stmt.data == 'assign':
                 assignments.append((stmt.children[0], stmt.children[1]))
@@ -175,6 +179,9 @@ class VerilogTransformer(Transformer):
                         s = cname
                         Line(c, cnode, Node(c, s))
                     if s not in c.forks:
+                        if f'{s}[0]' in c.forks:  # actually a 1-bit bus?
+                            s = f'{s}[0]'
+                        else:
                             log.warn(f'Signal not driven: {s}')
                             Node(c, s)  # generate fork here
                     fork = c.forks[s]
@@ -187,8 +194,11 @@ class VerilogTransformer(Transformer):
             if sd.kind == 'output':
                 for name in sd.names:
                     if name not in c.forks:
-                        log.warn(f'Output not driven: {name}')
+                        if f'{name}[0]' in c.forks:  # actually a 1-bit bus?
+                            name = f'{name}[0]'
                         else:
+                            log.warn(f'Output not driven: {name}')
+                            continue
                     Line(c, c.forks[name], c.cells[name])
         return c