Stefan Holst
351d809306
- Circuit: is now pickleable and comparable - Circuit: utilities for locating/indexing io-ports - Verilog: parser fixes, support yosys-style verilog - SDF: parser fixes, full XOR support - STIL: parser fixes - Simulators: faster, up to 4-input cells, pickleable - WaveSim: WSA calculation support - WaveSim: Per-simulation parameters and delays - Logic: Data are now raw numpy arrays - Logic: More tools for bit-packing - Added DEF parser - Better techlib support for NanGate, SAED, GSC180 - Tests and docs improvements
23 lines
674 B
Makefile
23 lines
674 B
Makefile
# pip install sphinx sphinx-rtd-theme
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#
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# Minimal makefile for Sphinx documentation
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#
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# You can set these variables from the command line, and also
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# from the environment for the first two.
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SPHINXOPTS ?=
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SPHINXBUILD ?= sphinx-build
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SOURCEDIR = .
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BUILDDIR = _build
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# Put it first so that "make" without argument is like "make help".
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help:
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@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
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.PHONY: help Makefile
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# Catch-all target: route all unknown targets to Sphinx using the new
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# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
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%: Makefile
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@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
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