A python module for parsing, processing, and simulating gate-level circuits.
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Stefan Holst
840b816804
Circuit pickle, STIL/SDF/techlib fixes, sdata
...
- fix pin indices for various SC lib variants
- SDF annotation improvements
- STIL loading improvements
- Support for per-simulation parameters in WaveSim
- Circuit is now pickleable and comparable
2 years ago
..
__init__.py
Project Import
4 years ago
b01.bench
Project Import
4 years ago
b01.v
Project Import
4 years ago
b14.sdf.gz
updated b14 benchmark, update wavesim capture api, expand usage examples
4 years ago
b14.stuck.stil.gz
updated b14 benchmark, update wavesim capture api, expand usage examples
4 years ago
b14.transition.stil.gz
updated b14 benchmark, update wavesim capture api, expand usage examples
4 years ago
b14.v.gz
updated b14 benchmark, update wavesim capture api, expand usage examples
4 years ago
conftest.py
Project Import
4 years ago
gates.sdf
Project Import
4 years ago
gates.v
Project Import
4 years ago
test_bench.py
Docs, __index__, fault injection and TechLib
4 years ago
test_circuit.py
Circuit pickle, STIL/SDF/techlib fixes, sdata
2 years ago
test_logic.py
Circuit pickle, STIL/SDF/techlib fixes, sdata
2 years ago
test_logic_sim.py
Circuit pickle, STIL/SDF/techlib fixes, sdata
2 years ago
test_sdf.py
Docs, __index__, fault injection and TechLib
4 years ago
test_stil.py
Circuit pickle, STIL/SDF/techlib fixes, sdata
2 years ago
test_verilog.py
New m-valued logic arrays, documentation, 0.0.2
4 years ago
test_wave_sim.py
Circuit pickle, STIL/SDF/techlib fixes, sdata
2 years ago