stefan/kyupy
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s-holst 7a6ab750ca Initial commit
2020-10-29 12:10:43 +09:00
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Initial commit
2020-10-29 12:10:43 +09:00
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Description
A python module for parsing, processing, and simulating gate-level circuits.
61 MiB
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Languages
Python 93.7%
Verilog 3.9%
Coq 2.4%