Stefan Holst
351d809306
- Circuit: is now pickleable and comparable - Circuit: utilities for locating/indexing io-ports - Verilog: parser fixes, support yosys-style verilog - SDF: parser fixes, full XOR support - STIL: parser fixes - Simulators: faster, up to 4-input cells, pickleable - WaveSim: WSA calculation support - WaveSim: Per-simulation parameters and delays - Logic: Data are now raw numpy arrays - Logic: More tools for bit-packing - Added DEF parser - Better techlib support for NanGate, SAED, GSC180 - Tests and docs improvements
13 lines
125 B
Plaintext
13 lines
125 B
Plaintext
__pycache__
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.ipynb_checkpoints
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.pytest_cache
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.DS_Store
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*.pyc
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docs/_build
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build
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dist
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.idea
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.vscode
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src/kyupy.egg-info
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*nogit*
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