Stefan Holst 0251d66d28 make circuit pickable and comparable

2021-03-28 19:35:19 +09:00

..

__init__.py

docs for numba and cuda

2021-01-16 13:35:20 +09:00

bench.py

TechLib class, remove unnecessary .index

2021-01-16 13:17:18 +09:00

circuit.py

make circuit pickable and comparable

2021-03-28 19:35:19 +09:00

logic_sim.py

initial letch support, fix capture in logic sim

2021-03-25 10:36:55 +09:00

logic.py

initial letch support, fix capture in logic sim

2021-03-25 10:36:55 +09:00

sdf.py

fix ff annotation

2021-01-22 18:03:18 +09:00

stil.py

fix parsing older stil files

2021-01-31 13:43:03 +09:00

techlib.py

initial letch support, fix capture in logic sim

2021-03-25 10:36:55 +09:00

verilog.py

doc and indent fix

2021-01-31 18:25:09 +09:00

wave_sim.py

TechLib class, remove unnecessary .index

2021-01-16 13:17:18 +09:00