A python module for parsing, processing, and simulating gate-level circuits.
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Stefan Holst 0251d66d28 make circuit pickable and comparable 4 years ago
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__init__.py docs for numba and cuda 4 years ago
bench.py TechLib class, remove unnecessary .index 4 years ago
circuit.py make circuit pickable and comparable 4 years ago
logic.py initial letch support, fix capture in logic sim 4 years ago
logic_sim.py initial letch support, fix capture in logic sim 4 years ago
sdf.py fix ff annotation 4 years ago
stil.py fix parsing older stil files 4 years ago
techlib.py initial letch support, fix capture in logic sim 4 years ago
verilog.py doc and indent fix 4 years ago
wave_sim.py TechLib class, remove unnecessary .index 4 years ago